A Cobalt Salicide CMOS Process with TiN-Strapped Polysilicon Gates

IEEE Electron Device Letters

Volumn 12, Issue 6, 1991, Pages 350-352

  Pfiester, James R ^a   Mele, Thomas C ^a   Limb, Young ^a   Jones, Robert E ^a   Woo, Michael ^a   Boeck, Bruce ^a   Gunderson, Craig D ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COBALT COMPOUNDS - APPLICATIONS; ELECTRODES; SEMICONDUCTING SILICON; TITANIUM COMPOUNDS - APPLICATIONS;

COBALT SALICIDE CMOS PROCESS; LOW SHEET RESISTANCE GATE ELECTRODE; SELF ALIGNED DRAIN JUNCTION; SOURCE-DRAIN REGIONS; STRAPPED POLYSILICON GATES;

SEMICONDUCTOR DEVICES, MOSFET;

EID: 0026170229     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.82084     Document Type: Article

References (6)

1. C. M. Osburn, M. Y. Tsai, S. Roberts, C. J. Luchese, and C. Y. Ting, in Proc. 1st Int. Symp. VLSI Sci. Technol., C. J. Dell'Oca and W. M. Bullis, Eds. Pennington, NJ: Electrochemical Society, 1982, p. 213.
2. R. Liu, D. Williams, and W. Lynch, “Mechanisms for process-induced leakage in shallow silicided junctions,” in IEDM Tech. Dig., 1986, p. 58.
3. S. J. Hillenius et al., “A symmetric submicron CMOS technology,” in IEDM Tech. Dig., 1986, p. 253.
4. S. Nygren and S. Johansson, “High-temperature effects on a CoSi2/poly-Si metal oxide semiconductor gate configuration,” J. Vac. Sci. Technol., vol. A8, p. 3011, 1990.
5. E. Broadbent, R. Irani, and A. Morgain, “Application of self-aligned CoSi2 interconnection in sub-micron CMOS transistors,” in Proc. IEEE VLSI Multilevel Interconnection Conf., 1988, p. 175.
6. R. Verhaar, A. Bos, J. Van Laarhoven, H. Kraaij, and R. Wolters, “Self-aligned CoSi2 and TiW(N) local interconnect in a submicron CMOS process,” in Proc. European Workshop Refractory Metals and Silicides, R. De Keersmaecker and K. Maex, Eds. Amsterdam: North Holland, 1989, p. 458.