A 10-ns 54 × 54-b Parallel Structured Full Array Multiplier with 0.5-μm CMOS Technology

IEEE Journal of Solid-State Circuits

Volumn 26, Issue 4, 1991, Pages 600-606

  Mori, Junji ^a   Nagamatsu, Masato ^a   Hirano, Masashi ^a   Tanaka, Shigeru ^a   Noda, Makoto ^a   Toyoshima, Yoshiaki ^a   Hashimoto, Kazuhiro ^a   Hayashida, Hiroyuki ^a   Maeguchi, Kenji ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, CMOS--DESIGN; MICROPROCESSOR CHIPS;

ARRAY MULTIPLIERS; CMOS TECHNOLOGY; FLOATING POINT PROCESSING; PARALLEL STRUCTURES;

COMPUTERS, MICROCOMPUTER;

EID: 0026136710     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.75061     Document Type: Article

References (5)

1. M. Nagamatsu et al., “A 15 ns 32 × 32-bit CMOS multiplier with an improved parallel structure,” in 1989 CICC Dig. Tech. Papers, 10.3.
2. L. Korn and S.-W. Fu, “A 1,000,000 transistor microprocessor,” in 1989 ISSCC Dig. Tech. Papers, pp. 54–55.
3. A. D. Booth, “A signed binary multiplication technique,” Quart. J. Mech. Appl. Math., vol. 4, part 2, 1951.
4. C. S. Wallace, “A suggestion for fast multipliers,” IEEE Trans. Electron. Comput., vol. EC-13, pp. 14–17, Feb. 1964.
5. M. Kakumu et al., “0.5 μm gate 1M SRAM with high performance at 3.3 V,” in 1989 VLSI Technology Dig. Tech. Papers, pp. 63–64.