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Volumn 12, Issue 3, 1991, Pages 108-110

A 55-V, 0.2-m Ω · cm2 Vertical Trench Power MOSFET

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC MEASUREMENTS; SEMICONDUCTOR DEVICE MANUFACTURE - ETCHING;

EID: 0026117912     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.75727     Document Type: Article
Times cited : (21)

References (14)
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  • 4
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    • C. A. T. Salama and J. G. Oakes, “Nonplanar power field-effect transistors,” IEEE Trans. Electron Devices, vol. ED-25, no. 10, 1222-1228, Oct. 1978.
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    • Salama, C.A.T.1    Oakes, J.G.2
  • 5
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    • An ultra-low on-resistance power MOSFET fabricated by using a fully self-aligned process
    • D. Ueda, H. Takagi, and G. Kano, “An ultra-low on-resistance power MOSFET fabricated by using a fully self-aligned process,” IEEE Trans. Electron Devices, vol. ED-34, no. 4, pp. 926-930, 1987.
    • (1987) IEEE Trans. Electron Devices , vol.ED-34 , Issue.4 , pp. 926-930
    • Ueda, D.1    Takagi, H.2    Kano, G.3
  • 6
    • 0018985713 scopus 로고
    • Modeling of the on-resistance of LDMOS, VDMOS, and VMOS power transistors
    • S. C. Sun and J. D. Plummer, “Modeling of the on-resistance of LDMOS, VDMOS, and VMOS power transistors,” IEEE Trans. Electron Devices, vol. ED-27, no. 2, 356-367, 1980.
    • (1980) IEEE Trans. Electron Devices , vol.ED-27 , Issue.2
    • Sun, S.C.1    Plummer, J.D.2
  • 7
    • 0024124571 scopus 로고
    • TDMOS—An ultra-low on-resistance power transistor
    • Dec.
    • S. Mukherjee, M. Kim, L. Tsou, and M. Simpson, “TDMOS—An ultra-low on-resistance power transistor,” IEEE Trans. Electron Devices, vol. 35, no. 12, p. 2459, Dec. 1988.
    • (1988) IEEE Trans. Electron Devices , vol.35 , Issue.12 , pp. 2459
    • Mukherjee, S.1    Kim, M.2    Tsou, L.3    Simpson, M.4
  • 8
    • 84939711724 scopus 로고
    • The effect of RIE etching in CHF 3 /CO 2 plasma and successive residual silicon damage removal on the contact resistance of Al-nSi and Alusil-nSi contacts
    • K. Shenai et al., “The effect of RIE etching in CHF 3 /CO 2 plasma and successive residual silicon damage removal on the contact resistance of Al-nSi and Alusil-nSi contacts,” in Proc. 7th Symp. Plasma Processing, vol. 88-22, G. S. Mathad, G. C. Schwartz, and D. W. Hess, Eds. Pennington, NJ: Electrochemical Soc., 1988, pp. 179-193.
    • (1988) Proc. 7th Symp. Plasma Processing , vol.88 , pp. 179-193
    • Shenai, K.1
  • 9
    • 0025503628 scopus 로고
    • Novel refractory contact and interconnect metallizations for high-voltage and smart-power applications
    • Oct.
    • K. Shenai, “Novel refractory contact and interconnect metallizations for high-voltage and smart-power applications,” IEEE Trans. Electron Devices, vol. 37, no. 10, pp. 2207-2221, Oct. 1990.
    • (1990) IEEE Trans. Electron Devices , vol.37 , Issue.10 , pp. 2207-2221
    • Shenai, K.1
  • 10
    • 0003610719 scopus 로고
    • MOS (Metal Oxide Semiconductor) Physics and Technology
    • E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology. New York: Wiley, 1982.
    • (1982) New York: Wiley
    • Nicollian, E.H.1    Brews, J.R.2
  • 12
    • 1442308497 scopus 로고
    • Optimum silicon and GaAs power field-effect transistors for advanced high-density, high-frequency power supply applications
    • May
    • K. Shenai, C. S. Korman, and B. J. Baliga, “Optimum silicon and GaAs power field-effect transistors for advanced high-density, high-frequency power supply applications,” in Tech. Papers 4th Int. High Frequency Power Conversion. Ventura, CA: Intertec Communications, May 1989, pp. 32-61.
    • (1989) Tech. Papers 4th Int. High Frequency Power Conversion. Ventura , pp. 32-61
    • Shenai, K.1    Korman, C.S.2    Baliga, B.J.3
  • 13
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    • Sept.
    • K. Shenai, R. S. Scott, and B. J. Baliga, “Optimum semiconductors for high-power electronics,” IEEE Trans. Electron Devices, vol. 36, pp. 1811-1823, Sept. 1989.
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    • Shenai, K.1    Scott, R.S.2    Baliga, B.J.3
  • 14
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    • A new vertical power MOSFET structure with extremely reduced on-resistance
    • Jan.
    • D. Ueda, H. Takagi, and G. Kano, “A new vertical power MOSFET structure with extremely reduced on-resistance,” IEEE Trans. Electron Devices, vol. ED-32, no. 1, pp. 2-6, Jan. 1985.
    • (1985) IEEE Trans. Electron Devices , vol.ED-32 , Issue.1 , pp. 2-6
    • Ueda, D.1    Takagi, H.2    Kano, G.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.