메뉴 건너뛰기




Volumn 12, Issue 3, 1991, Pages 128-130

Impurity Barrier Properties of Reoxidized Nitrided Oxide Films for Use with p+-Doped Polysilicon Gates

Author keywords

[No Author keywords available]

Indexed keywords

OXIDES - THIN FILMS; SEMICONDUCTING SILICON; TRANSISTORS, FIELD EFFECT;

EID: 0026117813     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.75733     Document Type: Article
Times cited : (35)

References (12)
  • 1
    • 0022027064 scopus 로고
    • Design tradeoffs between surface and buried-channel FETs
    • G. Hu and R. Bruce, “Design tradeoffs between surface and buried-channel FETs,” IEEE Trans. Electron Devices, vol. ED-32, p. 584, 1985.
    • (1985) IEEE Trans. Electron Devices , vol.ED-32 , pp. 584
    • Hu, G.1    Bruce, R.2
  • 3
    • 0024930239 scopus 로고
    • Study of boron penetration through thin oxide with p + polysilicon gate
    • J. Y.-C. Sun, C. Wong, Y. Taur, and C.-H. Hsu, “Study of boron penetration through thin oxide with p + polysilicon gate,” in Symp. VLSI Technology Dig., 1989, pp. 17-18.
    • (1989) Symp. VLSI Technology Dig. , pp. 17-18
    • Sun, J.Y.-C.1    Wong, C.2    Taur, Y.3    Hsu, C.-H.4
  • 4
    • 0024896106 scopus 로고
    • Flourine effect on boron diffusion of p + gate devices
    • J. Sung et al., “Flourine effect on boron diffusion of p + gate devices,” in IEDM Tech. Dig., 1989, 447-450.
    • (1989) IEDM Tech. Dig.
    • Sung, J.1
  • 5
    • 0024920290 scopus 로고
    • The influence of flourine on threshold voltage instabilities in p + polysilicon gated p-channel MOSFETs
    • F. Baker et al., “The influence of flourine on threshold voltage instabilities in p + polysilicon gated p-channel MOSFETs,” in IEDM Tech. Dig., 1989, pp. 443-446.
    • (1989) IEDM Tech. Dig. , pp. 443-446
    • Baker, F.1
  • 6
    • 0025474417 scopus 로고
    • The effects of boron penetration on p + polysilicon gated PMOS devices
    • J. Pfiester et al., “The effects of boron penetration on p + polysilicon gated PMOS devices,” IEEE Trans. Electron Devices, vol. 37, no. 8, pp. 1842-1851, 1990.
    • (1990) IEEE Trans. Electron Devices , vol.37 , Issue.8 , pp. 1842-1851
    • Pfiester, J.1
  • 7
    • 0025591291 scopus 로고
    • The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in BF 2 implanted p + gate p-channel MOSFETs
    • H. Tseng et al., “The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in BF 2 implanted p + gate p-channel MOSFETs,” in Symp. VLSI Technology Dig., 1990, pp. 111-112.
    • (1990) Symp. VLSI Technology Dig. , pp. 111-112
    • Tseng, H.1
  • 8
    • 0020749253 scopus 로고
    • Low pressure nitrided-oxide as a thin gate dielectric for MOSFETs
    • S. Wong et al., “Low pressure nitrided-oxide as a thin gate dielectric for MOSFETs,” J. Electrochem. Soc., vol. 130, no. 5, pp. 1139-1144, 1983.
    • (1983) J. Electrochem. Soc. , vol.130 , Issue.5 , pp. 1139-1144
    • Wong, S.1
  • 9
    • 84941864388 scopus 로고
    • Ultrathin reoxidized nitrided oxide prepared by rapid isothermal processing for advanced MOS devices
    • T. Hori and H. Iwasaki, “Ultrathin reoxidized nitrided oxide prepared by rapid isothermal processing for advanced MOS devices,” in Rapid Isothermal Processing, R. Singh, Ed., vol. 1189 SPIE, 1990, pp. 176-185.
    • (1990) Rapid Isothermal Processing , vol.1189 , pp. 176-185
    • Hori, T.1    Iwasaki, H.2
  • 10
    • 0025445407 scopus 로고
    • A physical model for boron penetration through thin gate oxides from p + polysilicon gates
    • J. Pfiester, L. Parrillo, and F. Baker, “A physical model for boron penetration through thin gate oxides from p + polysilicon gates,” IEEE Electron Device Lett., vol. 11, no. 6, pp. 247-249, 1990.
    • (1990) IEEE Electron Device Lett. , vol.11 , Issue.6 , pp. 247-249
    • Pfiester, J.1    Parrillo, L.2    Baker, F.3
  • 11
    • 0038416243 scopus 로고
    • Ambient and dopant effects on boron diffusion in oxides
    • C. Wong and F. Lai, “Ambient and dopant effects on boron diffusion in oxides,” Appl. Phys. Lett., vol. 48, pp. 1658-1660, 1986.
    • (1986) Appl. Phys. Lett. , vol.48 , pp. 1658-1660
    • Wong, C.1    Lai, F.2
  • 12
    • 0024170834 scopus 로고
    • Doping of n + and p + polysilicon gates in a dual-gate CMOS process
    • C. Wong et al., “Doping of n + and p + polysilicon gates in a dual-gate CMOS process,” in IEDM Tech. Dig., 1988, pp. 238-241.
    • (1988) IEDM Tech. Dig. , pp. 238-241
    • Wong, C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.