-
1
-
-
84939339182
-
A Josephson 4-bit processor for a prototype computer
-
June
-
H. Nakagawa, S. Kosaka, I. Kurosawa, M. Aoyagi, Y. Hamazaki, Y. Okada, and S. Takada, “A Josephson 4-bit processor for a prototype computer,” in Extended Abstracts 1989 Int. Superconductivity Electronics Conf., pp. 387–390, June 1989.
-
(1989)
Extended Abstracts 1989 Int. Superconductivity Electronics Conf.
, pp. 387-390
-
-
Nakagawa, H.1
Kosaka, S.2
Kurosawa, I.3
Aoyagi, M.4
Hamazaki, Y.5
Okada, Y.6
Takada, S.7
-
2
-
-
84939383550
-
A sub-ns Josephson 4-bit processor
-
June
-
S. Kotani, T. Imamura, and S. Hasuo, “A sub-ns Josephson 4-bit processor,” in Extended Abstracts 1989 Int. Superconductivity Electronics Conf., pp. 381–386, June 1989.
-
(1989)
Extended Abstracts 1989 Int. Superconductivity Electronics Conf.
, pp. 381-386
-
-
Kotani, S.1
Imamura, T.2
Hasuo, S.3
-
3
-
-
84915861097
-
Extended Abstracts 1989 Int. Superconductivity Electronics Conf.
-
June
-
Y. Hatano, S. Yano, H. Mori, H. Yamada, M. Hirano, and U. Kawabe, ‘‘A 4-bit Josephson data processor with dc output buffer,” in Extended Abstracts 1989 Int. Superconductivity Electronics Conf., pp. 375–380, June 1989.
-
(1989)
Extended Abstracts 1989 Int. Superconductivity Electronics Conf.
, pp. 375-380
-
-
Hatano, Y.1
Yano, S.2
Mori, H.3
Yamada, H.4
Hirano, M.5
Kawabe, U.6
-
4
-
-
20244388494
-
A 1 GOPS 8b Josephson digital signal processor
-
Feb.
-
S. Kotani, A. Inoue, T. Imamura, and S. Hasuo, “A 1 GOPS 8b Josephson digital signal processor,” in ISSCC Dig. Tech. Papers, pp. 148–149, Feb. 1990.
-
(1990)
ISSCC Dig. Tech. Papers
, pp. 148-149
-
-
Kotani, S.1
Inoue, A.2
Imamura, T.3
Hasuo, S.4
-
5
-
-
0024716878
-
A 1-kbit Josephson memory using variable threshold cells
-
Aug.
-
I. Kurosawa, H. Nakagawa, S. Kosaka, M. Aoyagi, and S. Takada, “A 1-kbit Josephson memory using variable threshold cells,” IEEE J. Solid-State Circuits, vol. 24, pp. 1034–1040, Aug. 1989.
-
(1989)
IEEE J. Solid-State Circuits
, vol.24
, pp. 1034-1040
-
-
Kurosawa, I.1
Nakagawa, H.2
Kosaka, S.3
Aoyagi, M.4
Takada, S.5
-
6
-
-
0024749138
-
570-ps 13-mW Josephson 1-kbit NDRO RAM
-
Oct.
-
S. Nagasawa, Y. Wada, M. Hidaka, H. Tsuge, I. Ishida, and S. Tahara, “570-ps 13-mW Josephson 1-kbit NDRO RAM,” IEEE J. Solid-State Circuits, vol. 24, pp. 1363–1371, Oct. 1989.
-
(1989)
IEEE J. Solid-State Circuits
, vol.24
, pp. 1363-1371
-
-
Nagasawa, S.1
Wada, Y.2
Hidaka, M.3
Tsuge, H.4
Ishida, I.5
Tahara, S.6
-
7
-
-
0020917916
-
Experiments on a cross-section of a Josephson RAM chip
-
W. H. Henkels, K. H. Brown, T. V. Rajeevakumar, L. Geppert, J. W. Allan, Y. H. Lee, and J. T. Yeh, “Experiments on a cross-section of a Josephson RAM chip,” in Proc. 1983 IEEE Int. Conf. Computer Design, pp. 570–573.
-
(1983)
Proc. 1983 IEEE Int. Conf. Computer Design
, pp. 570-573
-
-
Henkels, W.H.1
Brown, K.H.2
Rajeevakumar, T.V.3
Geppert, L.4
Allan, J.W.5
Lee, Y.H.6
Yeh, J.T.7
-
8
-
-
0025547358
-
A fully operational 1-kbit variable threshold Josephson RAM
-
June
-
I. Kurosawa, H. Nakagawa, M. Aoyagi, S. Kosaka, and S. Takada, “A fully operational 1-kbit variable threshold Josephson RAM,” in 1990 Symp. VLSI Circuits, Dig. Tech. Papers, pp. 67–68, June 1990.
-
(1990)
1990 Symp. VLSI Circuits, Dig. Tech. Papers
, pp. 67-68
-
-
Kurosawa, I.1
Nakagawa, H.2
Aoyagi, M.3
Kosaka, S.4
Takada, S.5
-
9
-
-
5944236443
-
Josephson cross-sectional model experiment
-
Apr.
-
M. B. Ketchen, D. J. Herrell, and C. J. Anderson, “Josephson cross-sectional model experiment,” J. Appl. Phys., vol. 57, pp. 2550–2574, Apr. 1985.
-
(1985)
J. Appl. Phys.
, vol.57
, pp. 2550-2574
-
-
Ketchen, M.B.1
Herrell, D.J.2
Anderson, C.J.3
-
10
-
-
0020599203
-
A Josephson full adder circuit using four-junction logic (4JL) gate
-
Tokyo, Japan
-
H. Nakagawa, E. Sogawa, S. Takada, and H. Hayakawa, “A Josephson full adder circuit using four-junction logic (4JL) gate,” in Proc. 14th Int. Conf. Solid State Devices, Tokyo, Japan, 1982; also Japan J. Appl. Phys., vol. 22, suppl. 22–1, pp. 447–450, 1983.
-
(1983)
Proc. 14th Int. Conf. Solid State Devices
, vol.22
, pp. 447-450
-
-
Nakagawa, H.1
Sogawa, E.2
Takada, S.3
Hayakawa, H.4
-
11
-
-
0022221411
-
A Josephson counter circuit with two-phase power supply
-
Aug.
-
H. Nakagawa, I. Kurosawa, S. Takada, and H. Hayakawa, “A Josephson counter circuit with two-phase power supply,” in Extended Abstracts 17th Conf. Solid State Devices and Materials, Tokyo, Japan, pp. 123–126, Aug. 1985.
-
(1985)
Extended Abstracts 17th Conf. Solid State Devices and Materials
, pp. 123-126
-
-
Nakagawa, H.1
Kurosawa, I.2
Takada, S.3
Hayakawa, H.4
-
12
-
-
0024717908
-
A Josephson 4-bit RALU for a prototype computer
-
Aug.
-
H. Nakagawa, S. Kosaka, H. Kawamura, I. Kurosawa, M. Aoyagi, Y. Hamazaki, Y. Okada, and S. Takada, “A Josephson 4-bit RALU for a prototype computer,” IEEE J. Solid-State Circuits, vol. 24, pp. 1076–1084, Aug. 1989.
-
(1989)
IEEE J. Solid-State Circuits
, vol.24
, pp. 1076-1084
-
-
Nakagawa, H.1
Kosaka, S.2
Kawamura, H.3
Kurosawa, I.4
Aoyagi, M.5
Hamazaki, Y.6
Okada, Y.7
Takada, S.8
-
13
-
-
0024628362
-
Josephson address control unit IC for a 4-bit Microcomputer prototype
-
Mar.
-
S. Kosaka, H. Nakagawa, H. Kawamura, Y. Okada, Y. Hamazaki, M. Aoyagi, I. Kurosawa, A. Shoji, and S. Takada, “Josephson address control unit IC for a 4-bit Microcomputer prototype,” IEEE Trans. Magnetics, vol. 25, pp. 789–794, Mar. 1989.
-
(1989)
IEEE Trans. Magnetics
, vol.25
, pp. 789-794
-
-
Kosaka, S.1
Nakagawa, H.2
Kawamura, H.3
Okada, Y.4
Hamazaki, Y.5
Aoyagi, M.6
Kurosawa, I.7
Shoji, A.8
Takada, S.9
-
14
-
-
84939341889
-
A Josephson 10-bit instruction ROM unit for a prototype computer
-
June
-
M. Aoyagi, H. Nakagawa, I. Kurosawa, Y. Okada, Y. Hamazaki, S. Kosaka, A. Shoji, and S. Takada, “A Josephson 10-bit instruction ROM unit for a prototype computer,” in Extended Abstracts 1989 Int. Superconductivity Electronics Conf., pp. 271–274, June 1989.
-
(1989)
Extended Abstracts 1989 Int. Superconductivity Electronics Conf.
, pp. 271-274
-
-
Aoyagi, M.1
Nakagawa, H.2
Kurosawa, I.3
Okada, Y.4
Hamazaki, Y.5
Kosaka, S.6
Shoji, A.7
Takada, S.8
-
15
-
-
0025475587
-
A Josephson 10-b instruction 128-word ROM unit
-
M. Aoyagi, H. Nakagawa, I. Kurosawa, S. Kosaka, Y. Okada, Y. Hamazaki, and S. Takada, “A Josephson 10-b instruction 128-word ROM unit,” IEEE J. Solid-State Circuits, vol. 25, pp. 971–978, 1990.
-
(1990)
IEEE J. Solid-State Circuits
, vol.25
, pp. 971-978
-
-
Aoyagi, M.1
Nakagawa, H.2
Kurosawa, I.3
Kosaka, S.4
Okada, Y.5
Hamazaki, Y.6
Takada, S.7
-
16
-
-
84941466938
-
A data RAM unit chip for a Josephson computer prototype
-
June
-
I. Kurosawa, H. Nakagawa, S. Kosaka, M. Aoyagi, Y. Hamazaki, Y. Okada, and S. Takada, “A data RAM unit chip for a Josephson computer prototype,” in Extended Abstracts 1989 Int. Superconductivity Electronics Conf., pp. 302–305, June 1989.
-
(1989)
Extended Abstracts 1989 Int. Superconductivity Electronics Conf.
, pp. 302-305
-
-
Kurosawa, I.1
Nakagawa, H.2
Kosaka, S.3
Aoyagi, M.4
Hamazaki, Y.5
Okada, Y.6
Takada, S.7
-
17
-
-
0039191994
-
New fabrication process for Josephson tunnel junctions with (niobium nitride, niobium) double-layered electrodes
-
Dec.
-
A. Shoji, F. Shinoki, S. Kosaka, M. Aoyagi, and H. Hayakawa, “New fabrication process for Josephson tunnel junctions with (niobium nitride, niobium) double-layered electrodes,” Appl. Phys. Lett., vol. 41, pp. 1097–1099, Dec. 1982.
-
(1982)
Appl. Phys. Lett.
, vol.41
, pp. 1097-1099
-
-
Shoji, A.1
Shinoki, F.2
Kosaka, S.3
Aoyagi, M.4
Hayakawa, H.5
-
18
-
-
0022442929
-
Nb/Al-oxide/Nb tunnel junctions for Josephson integrated circuits
-
Jan.
-
H. Nakagawa, K. Nakaya, I. Kurosawa, S. Takada, and H. Hayakawa, “Nb/Al-oxide/Nb tunnel junctions for Josephson integrated circuits,” Japan J. Appl. Phys., vol. 25, pp. L70-L72, Jan. 1986.
-
(1986)
Japan J. Appl. Phys.
, vol.25
, pp. L70-L72
-
-
Nakagawa, H.1
Nakaya, K.2
Kurosawa, I.3
Takada, S.4
Hayakawa, H.5
-
19
-
-
0023288535
-
3-Ops switching operation in all-Nb Josephson logic gates
-
Feb.
-
K. Kuroda, J. Nakano, M. Yuda, and M Ueki, “3-Ops switching operation in all-Nb Josephson logic gates,” Electron. Lett., vol. 23, pp. 163–165, Feb. 1987.
-
(1987)
Electron. Lett.
, vol.23
, pp. 163-165
-
-
Kuroda, K.1
Nakano, J.2
Yuda, M.3
Ueki, M.4
-
20
-
-
0020112260
-
Operating characteristics of Josephson four-junction logic (4JL) gate
-
Apr.
-
H. Nakagawa, E. Sogawa, S. Kosaka, S. Takada, and H. Hayakawa, “Operating characteristics of Josephson four-junction logic (4JL) gate,” Japan J. Appl. Phys., vol. 21, pp. L198-L200, Apr. 1982.
-
(1982)
Japan J. Appl. Phys.
, vol.21
, pp. L198-L200
-
-
Nakagawa, H.1
Sogawa, E.2
Kosaka, S.3
Takada, S.4
Hayakawa, H.5
-
21
-
-
0020126435
-
Moat-guarded Josephson SQUID’s
-
May
-
S. Bermon and T. Gheewala, “Moat-guarded Josephson SQUID’s,” IEEE Trans. Magnetics, vol. MAG-19, pp. 1160–1164, May 1983.
-
(1983)
IEEE Trans. Magnetics
, vol.19 MAG
, pp. 1160-1164
-
-
Bermon, S.1
Gheewala, T.2
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