Fabrication Process for a Josephson Computer ETL-JC1 Using Nb Tunnel Junctions

IEEE Transactions on Magnetics

Volumn 27, Issue 2, 1991, Pages 3109-3112

  Nakagawa, H ^a   Kurosawa, I ^a   Aoyagi, M ^a   Takada, S ^a  

^a ELECTROTECHNICAL LABORATORY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE, DIGITAL - RANDOM ACCESS; INTEGRATED CIRCUITS, LSI;

JOSEPHSON COMPUTERS; TUNNEL JUNCTIONS;

SUPERCONDUCTING DEVICES;

EID: 0026116750     PISSN: 00189464     EISSN: 19410069     Source Type: Journal    
DOI: 10.1109/20.133870     Document Type: Article

References (17)

1. M.Gurvitch, M. A. Washington, and H. A. Huggins, “High quality refractory Josephson tunnel junctions utilizing thin aluminum layers,” Appl. Phys. Lett. vol. 42, no. 5, pp. 472–474, Mar. 1983.
2. A.Shoji, M.Aoyagi, S.Kosaka, F.Shinoki, and H.Hayakawa, “Niobium nitride Josephson tunnel junctions with magnesium oxide barriers,” Appl. Phys. Lett. vol. 46, no. 11, pp.1098-1100, June 1985.
3. H. Kroger, L. N. Smith, and D. W. Jillie, “Selective niobium anodization process for fabricating Josephson tunnel junctions,” Appl. Phys. Lett. vol. 39, pp. 280–282, 1981.
4. S.Kotani, T.Imamura, and S.Hasuo, “A sub-ns Josephson 4-bit processor,” in Extended Abstr. 1989 Int. Superconductivity Electronics Conf. (ISEC‘89), Tokyo, pp.381-386, Jun. 1989.
5. Y.Hatano, S.Yano, H.Mori, H.Yamada, M.Hirano, and U.Kawabe, “A 4-bit Josephson data processor with dc output buffer,” in Extended Abstr, 1989 Int. Superconductivity Electronics Conf. (ISEC189), Tokyo, pp.375-380, Jun. 1989.
6. S.Kotani, A.Inoue, T.Imamura, and S.Hasuo, “A 1GOPS 8b Josephson digital signal processor,” in Digest of Technical Papers 1990 IEEE Int. Solid-State State Circuits Conference, pp.148-149, Feb. 1990.
7. S.Nagasawa, Y.Wada, M.Hidaka, H.Tsuge, I.Ishida, and S.Tahara, “570-ps 13-mW Josephson 1-kbit NDRO RAM,” IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1363–1371, Oct. 1989.
8. H.Suzuki, N.Fujimaki, H.Tamura, T.Imamura, and S.Hasuo, “A 4k Josephson memory,” IEEE Trans. Magn. vol. MAG-25, pp.783-788, Mar. 1989.
9. S.Takada, H.Nakagawa, I.Kurosawa, M.Aoyagi, S.Kosaka, Y.Okada, and Y.Hamazaki, “A multichip superconducting microcomputer ETL-JC1,” presented in this conference.
10. H.Nakagawa, K.Nakaya, I.Kurosawa, S.Takada, and H.Hayakawa, “Nb/Al-oxide/Nb tunnel junctions for Josephson integrated circuits,” Jpn. J. Appl. Phys. vol. 25, no. 1, pp. L70-L72, Jan. 1986.
11. K.Kuroda and M.Yuda, “Niobium-stress influence on Nb/Al-oxide/Nb Josephson junctions,” J. Appl. Phys. vol. 63, no. 7, pp. 2352–2357, Apr. 1988.
12. A.A.Bright, J.H.Greiner, S.P.Klepner, R.H.Wang, and A.J.Warnecke, “Thin film fabrication for the Josephson technology cross-sectional model,” J. Vac, Sci. Technol. B1(1), pp. 77–90, Jan.-Mar. 1983.
13. M.Aoyagi, H.Nakagawa, I.Kurosawa, S.Kosaka, Y.Okada, Y.Hamazaki, and S.Takada,“A Josephson 10-b instruction 128-word ROM unit,” IEEE J. Solid-State Circuits, vol. 25, no. 4, pp. 971–978, Aug. 1990.
14. I.Kurosawa, H.Nakagawa, M.Aoyagi, S.Kosaka, and S.Takada, “A fully operational 1-kbit variable threshold Josephson RAM,” in Digest of Technical Papers 1990 VLSI Circuits Symposium, pp. 67–68, Jun. 1990.
15. S.Kosaka, H.Nakagawa, H.Kawamura, Y.Okada, Y.Hamazaki, M.Aoyagi, 1.Kurosawa, A.Shoji, and S.Takada, “Josephson address control unit IC for a 4-bit microcomputer prototype,” IEEE Trans. Maps. vol. MAG-25, no. 2, pp. 789–794, Mar. 1989.
16. H.Nakagawa, S.Kosaka, H.Kawamura, I.Kurosawa, M.Aoyagi, Y.Hamazaki, Y.Okada, and S.Takada, “A Josephson 4-bit RALU for a prototype computer,” IEEE J. Solid-State Circuits, vol. 24, no. 4, pp. 1076–1084, Aug. 1989.
17. H.Nakagawa, S.Kosaka, I.Kurosawa, M.Aoyagi, Y.Hamazaki, Y.Okada, and S.Takada, “A Josephson 4-bit processor for a prototype computer,” in Extended Abstr. 1989 Int. Superconductivity Electronics Conf. (ISECT’89), Tokyo, pp.387-390, Jun. 1989.