Families of reed-muller canonical forms

International Journal of Electronics

Volumn 70, Issue 2, 1991, Pages 259-280

  Green, D H ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

MATHEMATICAL TECHNIQUES--MATRIX ALGEBRA;

MODULAR CIRCUIT TREE; NESTED HIERARCHY; RECURSIVELY DEFINED INCIDENCE MATRICES; REED - MULLER CANONICAL FORMS; SWITCHING FUNCTIONS; TRUTH VECTOR;

SWITCHING THEORY;

EID: 0026111177     PISSN: 00207217     EISSN: 13623060     Source Type: Journal    
DOI: 10.1080/00207219108921277     Document Type: Article

References (17)

1. Besslich, P. W., 1983, Efficient computer method for EXOR logic design. Proceedings of the institution of Electrical Engineers, 130, 203-206.
2. Bioul, G., and Davio, M., 1972, Taylor expansions of Boolean functions and their derivatives. Philips Research Reports 27, 1-6.
3. Cohn, M, 1962, Inconsistent canonical forms of switching functions. i.R.E. Transactions Electronic Computers, 11, 284-285.
4. Davio, M., Deschamps, J.-P., and Thayse, A., 1978, Discrete and Switching Functions (St. Sephorin, Switzerland: Georgi).
5. Gkeen, D. H., 1989, Ternary Reed-Muller switching functions with fixed and mixed polarities. International Journal of Electronics 67, 761-775;
6. Gkeen, D. H 1990a, Reed-Muller expansions with fixed and mixed polarities over GF(4). Proceedings of the Institution of Electrical Engineers, Pt E, 137, 380-388;
7. Gkeen, D. H 1990b, Reed-Muller canonical forms with mixed polarity and their manipulations. Proceedings of the Institution of Electrical Engineers., 137, 103-113.
8. Gkeen, D. H., and Edkins, M., 1978, Synthesis procedures for switching circuits represented in generalised Reed-Muller form over a finite field. Computers and Digital Techniques, 1, 27-35.
9. Green, D. H., and Taylor, I. S., 1976, Multiple-valued switching circuit design by means of generalised Reed-Muller expansions. Digital Processes, 2, 63-81.
10. Kantopoulos, S. V., 1980, Classification of exclusive-OR structures in the minimisation of logic functions, international Journal of Electronics, 49, 115-129.
11. Kodandapani, K. L., and Setlur, R. V., 1975, Reed-Muller canonical forms in multivalued logic. I.E.E.E, Transactions on Computer, 24, 628-635.
12. Lorn, Z. M., Aoulad-Syad, D., and Tosser, A. J., 1979, Determination of the set of irredundant modulo-2 sums-of-products expression of a logic function. Proceedings of the Institution of Electrical Engineers, Pt E, 2, 2-6.
13. Lui, P. K., and Muzio, J. C., 1990, Simplified theory of Boolean functions, international Journal of Electronics, 68, 329-341.
14. Mukhopadhyay, A., and Schmitz, G., 1970, Minimisation of exclusive-OR and logical equivalence switching circuits. I.E.E.E. Transactions on Computers, 19, 132-140.
15. Reddy, S. M., 1972, Easily testable realisations for logic functions. I.E.E.E. Transactions on Computers, 21, 1183-1188.
16. Than, A., 1987, Graphical method for the conversion of minterms to Reed-Muller coefficients and the minimisation of exclusive-OR switching functions. Proceedings of the institution of Electrical Engineers, PtE, 134, 93-99
17. Zhang, Y. Z., and Rayner, P. J. W., 1984, Minimisation of Reed-Muller polynomials with fixed polarity. Proceedings of the Institution of Electrical Engineers, PtE, 131, 177-186.