Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding

IEEE Transactions on Computers

Volumn 40, Issue 2, 1991, Pages 178-195

  Parhi, Keshab K ^a   Messerschmitt, David G ^b  

^a UNIVERSITY OF MINNESOTA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

deterministic; Full static rate optimal schedules; intra interation and inter iteration precedence constraints; iteration bound; nonpreemptive multiprocessor schduling; optimum unfolding; perfect rate data flow programs; periodic; processor bounds; program unfolding; retiming real time signal and image processing; static data flow programming

Indexed keywords

COMPUTER METATHEORY--PROGRAMMING THEORY; OPTIMIZATION--APPLICATIONS; SCHEDULING--APPLICATIONS;

COMPUTATIONAL MODELS; DATA-FLOW PROGRAMS;

COMPUTER SYSTEMS, DIGITAL;

EID: 0026108176     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.73588     Document Type: Article

References (38)

1. R. E. Karp and R. E. Miller, “Properties of a model for parallel computations: Determinacy, termination, and queueing,” SIAM J. Appl. Math., vol. 14, no. 6, pp. 1390–1411, Nov. 1966.
2. R. Reiter, “Scheduling parallel computations,” J. ACM, vol. 15, no. 4, pp. 590–599, Oct. 1968.
3. R. E. Crochiere and A. V. Oppenheim, “Analysis of linear digital networks,” Proc. IEEE, vol. 63, no. 4, pp. 581–595, Apr. 1975.
4. J.B. Dennis, “Data flow supercomputers,” IEEE Comput. Mag., pp. 48–56, Nov. 1980.
5. A. L. Davis and R. M. Keller, “Data flow program graphs,” IEEE Comput. Mag., vol. 15, no. 2, pp. 26–41, Feb. 1982.
6. W. B. Ackerman, “Data flow languages,” IEEE Comput. Mag., vol. 15, no. 2, pp. 15–25, Feb. 1982.
7. E.A. Lee and D. G. Messerschmitt, “Static scheduling of synchronous data flow programs for digital signal processing,” IEEE Trans. Comput., vol. C-36, no. 1, pp. 24–35, Jan. 1987.
8. S. Y. Kung, P. S. Lewis, and S. C. Lo, “Performance analysis and optimization of VLSI data flow arrays,” J. Parallel Distributed Comput., vol. 4, pp. 592–618, 1987.
9. K. K. Parhi and D. G. Messerschmitt, “Rate-optimal fully - static multiprocessor scheduling of data-flow signal processing programs,” in Proc. 1989 IEEE Int. Symp. Circuits Syst., Portland, OR, May 1989
10. —, “Fully-static rate-optimal scheduling of iterative data-flow programs via optimum unfolding,” in Proc. 1989 Int. Conf. Parallel Processing, St. Charles, IL, Aug. 1989
11. S.C. Cheng, J.A. Stankovic, and K. Ramamritham, “Scheduling algorithms for hard real-time systems-A brief survey,” in Hard Real-Time Systems Tutorial, J. A. Stankovic, Ed. New York: IEEE Computer Society Press, 1988, pp. 150–173.
12. C. L. Liu and J.W. Layland, “Scheduling algorithms for multiprogramming in a hard real-time environment,” J. ACM, vol. 20, pp. 46–61, 1973.
13. E. L. Lawler and C. U. Martel, “Scheduling periodically occurring tasks on multiple processsors,” Inform. Processing Lett., vol. 12, pp. 9–12, 1981.
14. W. Zhao, K. Ramamritham, and J.A. Stankovic, “Preemptive scheduling under time and resource constraints,” IEEE Trans. Comput., pp. 949–960, Aug. 1987.
15. J. W. S. Liu et. al., “Scheduling real-time, periodic jobs using imprecise results,” in Proc. IEEE Real-Time Syst. Symp., San Jose, CA, Dec. 1987, pp. 252–260.
16. E. G. Coffman, Jr., Ed., Computer and Job Scheduling Theory. New York: Wiley, 1976.
17. D.A. Schwartz and T. P. Barnwell, III, “A graph theoretic technique for the generation of systolic implementations for shift invariant flow graphs,” in Proc. ICASSP-84, San Diego, CA, Mar. 1984.
18. D.A. Schwartz, “Synchronous multiprocessor realizations of shift invariant flow graphs,” Ph.D. dissertation, Georgia Insdt. Technol., Tech. Rep. DSPL-85-2, July 1985.
19. D.A. Schwartz and T. P. Barnwell, III, “Cyclostatic multiprocessor scheduling for the optimal implementation of shift invariant flow graphs,” in Proc. 1CASSP-85, Tampa, FL, Mar. 1985.
20. D.A. Schwartz, “Cyclo-static realizations: Loop unrolling and CPM, optimal multiprocessor scheduling,” in Proc. 1987 Princeton Workshop Algorithms, Architecture, and Technology Issues in Models of Concurrent Computations, Sept. 30-Oct. 1, 1987.
21. S. H. Lee and T. P. Barnwell, III, “Optimal multiprocessor implementation from a serial algorithm specification,” in Proc. ICASSP-88, NY, Apr. 1988, pp. 1694–1697.
22. H. Forren and D. A. Schwartz, “Transforming periodic synchronous multiprocessor programs,” in Proc. ICASSP-87, Dallas, TX, Apr. 1987, pp. 1406–1409.
23. M. Renfors and Y. Neuvo, “The maximum sampling rate of digital filters under hardware speed constraints,” IEEE Trans Circuits Syst., vol. CAS-28, no. 3, pp. 196–202, Mar. 1981.
24. T. P. Barnwell, III and C. J. M. Hodges, “Optimal implementation of signal flow graphs on synchronous multiprocessors,” in Proc. 1982 Int. Conf. Parallel Processing, Belaire, MI, Aug. 1982.
25. C. V. Ramamoorthy and G.S. Ho, “Performance evaluation of asynchronous concurrent systems using Petri nets,” IEEE Trans. Software Eng., vol. SE-6, no. 5, pp. 440–449, Sept. 1980.
26. J. P. Brafman, J. Szczupak, and S. K. Mitra, “An approach to implementation of digital filters using microprocessors,” IEEE Trans. Acoust., Speech, Signal Processing, vol. 26, no. 5, pp. 442–446, Oct. 1978.
27. J. Zeman and G.S. Moschytz, “Systematic design and programming of signal processors using project management techniques,” IEEE Trans. Acoust., Speech, Signal Processing, vol. 31, no. 6, pp. 1536–1549, Dec. 1983.
28. C.E. Leiserson, F. Rose, and J. Saxe, “Optimizing synchronous circuitry by retiming,” in Proc. Third Caltech Conf VLSI, Pasadena, CA, Mar. 1983, pp. 87–116.
29. S.Y. Kung, “On supercomputing with systolic/wavefront array processors,” Proc. IEEE, vol. 72, no. 7, July 1984.
30. K.K. Parhi and D. G. Messerschmitt, “Concurrent cellular VLSI adaptive filter architectures,” IEEE Trans. Circuits Syst., pp. 1141–1152, Oct. 1987.
31. —, “Pipelining and parallelism in recursive digital filters, Part II,” IEEE Trans. Acoust., Speech, Signal Processing, pp. 1118–1135, July 1989.
32. M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of the NP-Completeness. San Francisco, CA: Freeman, 1979.
33. K. K. Parhi, “Algorithm transformations for concurrent processors,” Proc. IEEE, vol. 77, no. 12, pp. 1879–1895, Dec. 1989.
34. T. C. Hu, “Parallel sequencing and assembly line problems,” Oper. Res., vol. 9, pp. 841–848, 1961.
35. M. C. McFarland et. al., “High level synthesis of digital systems,” Proc. IEEE, Feb. 1990.
36. K.K. Parhi, “Nibble-serial arithmetic processor designs via unfolding,” in Proc. IEEE Int. Symp. Circuits Syst., May 1989, OR, pp. 635–640.
37. C.-Y. Wang and K. K. Parhi, “Digit-serial DSP architectures,” in Proc. IEEE Conf Application Specific Array Processors, Princeton, NJ, Sept. 1990.
38. K. K. Parhi, “A systematic approach for design of digitserial signal processing architectures,” IEEE Trans. Circuits Syst., to be published.