A Macromodeling Algorithm for Analog Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 10, Issue 2, 1991, Pages 150-160

  Casinovi, Giorgio ^a   Sangiovanni Vincentelli, Alberto ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORKS--ANALYSIS; INTEGRATED CIRCUITS--COMPUTER AIDED ANALYSIS;

ANALOG CIRCUITS; MACROMODELING ALGORITHMS;

COMPUTER PROGRAMMING;

EID: 0026103935     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.68402     Document Type: Article

References (27)

1. G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of integrated circuit operational amplifiers,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 353–363, 1974.
2. I. E. Getreu, A. D. Hadiwidjaja, and J. M. Brinch, “An integrated-circuit comparator macromodel,” IEEE J. Solid-State Circuits, vol. SC-11, pp. 826–833, 1976.
3. C. Turchetti and G. Masetti, “A macromodel for integrated all-MOS operational amplifiers,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 389–394, 1983.
4. J. Ousterhout, “Switch-level delay models for digital MOS VLSI,” in Proc. 21st Design Automation Conf., June 1984, pp. 542–548.
5. T. Lin and C. A. Mead, “Signal delay in general RC networks with application to timing simulation of digital integrated circuits,” in Proc. Conf. on Advanced Research in VLSI, MIT, Jan. 1984, pp. 93–99.
6. T. Tokuda etal., “Delay-time modeling for ED MOS logic LSI,” IEEE Trans. Computer-Aided Design, vol. CAD-2, pp. 129–134, 1983.
7. M. D. Matson, “Macromodeling of digital MOS VLSI circuits,” MIT Tech. Rep. VLSI Memo No. 84–212, Nov. 1984.
8. S. R. Nassif and S. W. Director, “WASIM: A waveform based simulator for VLSICs,” in Proc. 1985 Int. Conf. on Computer-Aided Design, Nov. 1985, pp. 29–31.
9. W. M. Coughran, Jr., E. Grosse, and D. J. Rose, “CAzM: A circuit analyzer with macromodeling,” IEEE Trans. Electron. Devices, vol. ED-30, pp. 1207–1213, 1983.
10. C. Visweswariah, R. Chadha, and C. Chen, “Model development and verification for high level analog blocks,” in Proc. 25th Design Automation Conf., June 1988, pp. 376–382.
11. G. Casinovi, “Macromodeling for the simulation of large scale analog integrated circuits,” Ph.D. dissertation, Univ. of California, Berkeley, June 1988.
12. J. M. Ortega and W. C. Rheinboldt, Iterative Solution of Nonlinear Equations in Several Variables. New York: Academic, 1970.
13. A. E. Bryson, Jr. and Y. Ho, Applied Optimal Control. Waltham, MA: Ginn, 1969.
14. G. M. Smirnov, Oscillation Theory of Optimal Processes. New York: Wiley, 1984.
15. R. Gonzalez and E. Rofman, “On bang-bang control policies,” in Optimization Techniques, Part 2, J. Cea, ed. New York: Springer-Verlag, 1976, pp. 587–602.
16. G. D. Hachtel and R. A. Rohrer, “Techniques for the optimal design and synthesis of switching circuits,” Proc. IEEE, vol. 55, pp. 1864–1877, 1967.
17. R. K. Brayton and R. Spence, Sensitivity and Optimization. Amsterdam, The Netherlands: Elsevier, 1980.
18. G. Casinovi, “Input-output approximations of dynamical systems,” presented at 1989 IFAC Nonlinear Control Systems Design Symposium, Capri, Italy, June 14–16, 1989.
19. R. A. Rohrer, “Fully automated network design by digital computer: Preliminary considerations,” Proc. IEEE, vol. 55, pp. 1929–1939, 1967.
20. C. de Boor, A Practical Guide to Splines. New York: Springer-Verlag, 1978.
21. C. G. Broyden, “A class of methods for solving nonlinear simultaneous equations,” Math. Comput., vol. 19, no. 92, pp. 577–593, 1965.
22. A. S. Householder, The Theory of Matrices in Numerical Analysis. New York: Blaisdell, 1964.
23. M. Avriel, Nonlinear Programming: Analysis and Methods. Englewood Cliffs, NJ: Prentice-Hall, 1976.
24. T. L. Quarles, “SPICE3 version 3cl user's guide,” Tech. Rep. UCB/ERL M89/46, Univ. of California, Berkeley, 1989.
25. L. J. Borg-Graham, “Modelling the somatic electrical response of hippocampal pyramidal neurons,” Master's thesis, Massachusetts Institute of Technology, May 1987.
26. J. Doernberg, “High speed analog-to-digital conversion using 2-step flash architectures,” Tech. Rep. UCB/ERL M89/46, Univ. of California, Berkeley, 1989.
27. S. W. Director and R. A. Rohrer, “The generalized adjoint network and network sensitivities,” IEEE Trans. Circuit Theory, vol. CT-16, pp. 318–323, 1969.