Evaluation of Delay-Time Degradation of Low-Voltage BiCMOS Based on a Novel Analytical Delay-Time Modeling

IEEE Journal of Solid-State Circuits

Volumn 26, Issue 1, 1991, Pages 25-31

  Fujishima, Minoru ^a   Asada, Kunihiro ^a   Sugano, Takuo ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR DEVICES, BIPOLAR - APPLICATIONS; SEMICONDUCTOR DEVICES, MOS - APPLICATIONS;

ANALYTICAL DELAY-TIME MODELING; BINMOS CIRCUITS; CBICMOS CIRCUITS; DELAY TIME DEGRADATION; LOW-VOLTAGE BICMOS; TOTEM POLE BICMOS;

INTEGRATED CIRCUITS;

EID: 0025948684     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.65706     Document Type: Article

References (13)

1. H. Lin, J. Ho, R. Iyer, and K. Kwong, “Complementary MOS-bipolar transistor structure,” IEEE Trans. Electron Devices, vol. ED-16, pp. 945–951, Nov. 1969.
2. I. Masuda, Y. Nishio, and T. Ikeda, “High-speed logic circuits combining bipolar and CMOS technology,” Trans. Inst. Electron Commun. Eng. Japan, vol. J67-C, pp. 999–1005, Dec. 1984 (in Japanese).
3. H. Momose, K. Cham, C. Drowley, H. Grinolds, and H. Fu, “0.5 micron BICMOS technology,” in IEDM Tech. Dig., 1987, pp. 838–840.
4. A. Watanabe, T. Nagano, S. Shukuri, and T. Ikeda, “Future BiCMOS technology for scaled supply voltage,” in IEDM Tech. Dig., 1989, pp. 429–432.
5. T. Douseki and Y. Ohmori, “BiCMOS circuit technology for a high-speed SRAM,” IEEE J. Solid-State Circuits, vol. 23, no. 1, pp. 68–73, Feb. 1988.
6. M. Fujishima, K. Asada, and T. Sugano, “Complementary BiCMOS circuit using merged device structure,” Trans. Inst. Electron Inform. Commun. Eng. Japan, vol. J72-C-II, no. 12, pp. 1171–1174, Dec. 1989 (in Japanese).
7. H. Shin et al., “Full-swing complementary BiCMOS logic circuits,” in BCTM Tech. Dig., 1989, pp. 229–232.
8. H. Shin, “Performance comparison of driver configurations and full-swing techniques for BiCMOS logic circuits,” IEEE J. Solid-State Circuits, vol. 25, no. 3, pp. 863–865, June 1990.
9. H. Shin, “Full-swing complementary BiCMOS logic circuits,” in Symp. VLSI Circuits Tech. Dig., 1990, pp. 89–90.
10. N. Weate and K. Eshraghian, Principles of CMOS VLSI Design: A System Perspective. Reading, MA: Addison-Wesley, 1985.
11. M. Suzuki, S. Tachibana, and H. Higuchi, “Performance and structures of scaled-down bipolr devices merged with CMOS-FET’s,” in IEDM Tech. Dig. 1984, pp. 694–697.
12. G. Rosseel and R. Dutton, “Influence of device parameters on the switching speed of BiCMOS buffers,” IEEE J. Solid-State Circuits, vol. 24, no. 1, pp. 90–99, Feb. 1989.
13. A. Vladimirescu and S. Liu, “The simulation of MOS integrated circuits using SPICE2,” Electron Res. Lab., Univ. of Calif., Berkeley, Memo. UCB/ERL M80/7, Feb. 1980.