Electrical Transient Study of Negative Resistance in SOI MOS Transistors

Electronics Letters

Volumn 26, Issue 1, 1990, Pages 73-74

  Le Neel O ^a   Haond, M ^b  

^a Matra MHS   (France)

^b ORANGE LABS   (France)

Author keywords

devices; materials; MOS structures; Negative resistance; Semiconductor devices; Transistors

Indexed keywords

SEMICONDUCTOR DEVICES, MOS--ELECTRIC CONDUCTIVITY;

MOS TRANSISTORS; SOI FILMS; SUBMICRON CMOS TECHNOLOGIES;

TRANSISTORS, FIELD EFFECT;

EID: 0025699582     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19900048     Document Type: Article

References (6)

1. Sharma, D. K., Gautier, J., and Merckel, G.: ‘Negative dynamic resistance in MOS devices’, IEEE J. Solid-State Circ, 1978, SC-13, pp. 378-380.
2. Sharma, D. K., and Ramanathan, K. V.: ‘Modeling thermal effects on MOS I/V characteristics’, IEEE Electron Dev. Lett., 1983, EDL-4, pp. 363-364.
3. Haond, M.: ‘unpublished results.
4. Mcdaid, L. J., Halls, S., Mellor, P. H., Eccleston, W., and Alderman, J. C.: ‘Physical origin of negative differential resistance in SOI transistors’, Electron. Lett., 1989, 25, pp. 827-828.
5. Haond, M., Dutartre, D., Bensahel, D., Monroy-Aguirre, A., Touret, S., and Chapuis, D.: ‘CMOS devices and circuits made in lamp-ZMR SOI films’, Microelectron. Eng., 1988, 8, pp. 201-218.
6. Haond, M., Le Neel, O., Gonchond, J. P., and Mascarin, G.: ‘Gate oxide breakdown voltage in SOI CMOS process using MESA isolation’. 19th Europ. solid-state dev. res. conf., Berlin, 1989.