SST-BiCMOS technology with 130 ps CMOS and 50 ps ECL

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1990, Pages 85-86

  Kobayashi, Yoshiji ^a   Yamaguchi, Chikara ^a   Shimoyama, Nobuhiro ^a   Tanabe, Yasuyuki ^a   Miura, Kenji ^a   Nakajima, Shigeru ^a   Imai, Kazuo ^a   Sakai, Tetsushi ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BI-CMOS; BIPOLAR TECHNOLOGY; DEVICE PERFORMANCE; EMITTER COUPLED LOGIC; LIGHTLY-DOPED DRAINS; MOS TECHNOLOGY; N-P-N TRANSISTORS; POLYSILICON LAYERS; PROPAGATION DELAY TIME; SELF-ALIGNED; SINGLE CHIPS;

BICMOS TECHNOLOGY; CUTOFF FREQUENCY; POLYSILICON; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICES, MOS; TRANSISTORS, BIPOLAR;

TECHNOLOGY; LOGIC CIRCUITS, EMITTER COUPLED;

BICMOS; DIGEST OF PAPER; NPN TRANSISTORS; POLYSILICON;

EID: 0025671536     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.1990.111020     Document Type: Conference Paper

References (2)

1. M.Matsui et al., ISSCC Dig. p38('89)
2. S.Konaka et al., 19th ICSSDM p331('87)