Merged complementary BiCMOS for logic applications

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1990, Pages 81-82

  Ogura, S ^a   Rovedo, N ^a   Acocella, J ^a   Dally, A ^a   Yanagisawa, T ^a   Burkhardt, J ^a   Buti, T ^a   Richwine, C ^a   Montegari, F ^a   Barnes, K ^a   Ng, C ^a   Valsamakis, E ^a   Codella, C ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BI-CMOS; DEVICE STRUCTURES; EMITTER FOLLOWERS; LOGIC APPLICATIONS; PROCESS COMPLEXITY; TEST CIRCUIT; VERTICAL PNP;

BICMOS TECHNOLOGY; VLSI CIRCUITS; INTEGRATED CIRCUITS, CMOS; TRANSISTORS, BIPOLAR; TRANSISTORS, FIELD EFFECT;

LOGIC CIRCUITS;

BICMOS LOGIC; BIPOLAR-FET DEVICES; COMPLEMENTARY BICMOS; DIGEST OF PAPER; VERTICAL PNP;

EID: 0025635255     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.1990.111018     Document Type: Conference Paper

References (2)

1. Pleshko, P.,"MOSBIP switching circuit", U.S. Patent 3,879,619, April 1975.
2. Sunaga, T., "Merged Bipolar-CMOS Device", IBM Technical Disclosure Bulletin, Vol. 28, No. 8 (1986), 3S58-3561.