An interactive two-level architecture for a memory network pattern classifier

Pattern Recognition Letters

Volumn 11, Issue 8, 1990, Pages 537-540

  Fairhurst, M C ^a   Wahab, H M S Abdel ^a  

^a UNIVERSITY OF KENT   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

MEMORY NETWORK PATTERN CLASSIFIER; MULTI-LEVEL ARCHITECTURE; PROCESSING LAYER;

EID: 0025620604     PISSN: 01678655     EISSN: None     Source Type: Journal    
DOI: 10.1016/0167-8655(90)90022-T     Document Type: Article

References (12)

1. A two-layer memory network architecture for a pattern classifier
2. Performance comparisons in hierarchical architectures for memory network pattern classifiers
3. Configuration selection for two-layer memory network pattern classifiers
4. A classification for alpha-numeric characters based on learning network techniques
5. An approach to performance optimisation in frequency-weighted memory network pattern classifiers
6. An analysis of discriminatory mechanisms in frequency-weighted memory array pattern classifiers
7. An analytical approach to the assessment and design of n-tuple pattern classifiers
8. Bibliography of estimation of misclassification
9. Recent advances in error rate estimation
10. Multi-level interaction in hierarchically structured pattern classifier architectures