Lower submicron FCBiMOS (fully complementary BiMOS) process with RTP and MeV implanted 5 GHz vertical PNP transistor

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1990, Pages 79-80

  Maeda, T ^a   Ishimaru, K ^a   Momose, H ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BI-CMOS PROCESS; COMPLEMENTARY BIPOLAR; CURRENT GAINS; DEVICE APPLICATION; DEVICE CHARACTERISTICS; EPITAXIAL WAFERS; HIGH CURRENT GAIN; HIGH DOSE; KEY TECHNOLOGIES; PNP TRANSISTORS; PROCESS INTEGRATION; SECONDARY DEFECT; SUBMICRON; VERTICAL PNP;

BICMOS TECHNOLOGY; BORON; EPITAXIAL GROWTH; RAPID THERMAL PROCESSING; SEMICONDUCTOR DEVICES, MOS; SEMICONDUCTOR MATERIALS; TRANSISTORS, BIPOLAR--MICROWAVES;

ION IMPLANTATION; INTEGRATED CIRCUITS, CMOS;

BIMOS; DIGEST OF PAPER; FULLY COMPLEMENTARY BIMOS; PNP TRANSISTORS;

EID: 0025591295     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.1990.111017     Document Type: Conference Paper

References (6)

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5. A. Tamba et al., SSDM, p.141 (1988)
6. T. Maeda et al., BCTM, p.102 (1989)