A 100-MHz 64-Tap FIR Digital Filter in 0.8-μm BiCMOS Gate Array

IEEE Journal of Solid-State Circuits

Volumn 25, Issue 6, 1990, Pages 1494-1501

  Gass, Wanda ^a   Yang, Paul T ^b   Shah, Ashwin H ^a  

^a TEXAS INSTRUMENTS   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, CMOS--DESIGN; LOGIC DEVICES--GATES;

BICMOS CIRCUITS; DIGITAL SIGNAL PROCESSING; FIR DIGITAL FILTER; GATE ARRAY TECHNOLOGY;

ELECTRIC FILTERS, DIGITAL;

EID: 0025559464     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.62185     Document Type: Article

References (11)

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10. M. Ishikawa et al., “Automatic layout synthesis for FIR filters using a silicon compiler,” in Proc. IEEE Int. Symp. Circuits Syst., 1990, pp. 2588–2591.
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