AC/DC Characterization of NMOS and PMOS Hot-Carrier-Induced Degradation Under AC/DC Stress

IEEE Transactions on Electron Devices

Volumn 37, Issue 11, 1990, Pages 2416-2419

  Dawes, Mary ^a   Alavi, Mohsen ^a   Kim, Dae M ^b  

^a INTEL CORPORATION   (United States)

^b TEKTRONIX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAILURE ANALYSIS; SEMICONDUCTOR MATERIALS - HOT CARRIERS; STRESSES;

HOT CARRIERS; NMOS TRANSISTORS;

TRANSISTORS;

EID: 0025516802     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.62305     Document Type: Article

References (13)

1. C. Hu, S. C. Tarn, F.-C. Hsu, P. Ko, T. Chan, and K. W. Terrill, “Hot-electron induced MOSFET degradation-Model, monitor, and improvement,” IEEE Trans. Electron Devices, vol. ED-32, no. 2, pp. 375-385, 1985.
2. M. Koyanagi, A. G. Lewis, R. A. Martin, T. Huang, and J. Chen. “Hot-electron-induced punchthrough (HEIP) effect in submicrometer PMOSFETs',” IEEE Trans. Electron Devices, vol. ED-34, no. 4, pp. 839-844, 1987.
3. T. Tsuchiya, “Trapped-electron and generated interface-trap effects in hot-electron-induced MOSFET degradation,” IEEE Trans. Electron Devices, vol. ED-34, no. 11, pp. 2291-2296, 1987.
4. J.J. Tzou, C. C. Yao, R. Cheung, and H. W. K. Chen, “Hot carrier-induced degradation in p-channel LDD MOSFETs',” IEEE Electron Device Lett., vol. EDL-7, no. 1, pp. 5-7, 1986.
5. K. K. Ng and G. W. Taylor, “Effects of hot-carrier trapping in n- and p-channel MOSFETs',” IEEE Trans. Electron Devices, vol. ED-30, no. 8, pp. 871-876, 1983.
6. K. M. Cham, H. Fu, and Y. Nishi, “The dependence of hot carrier degradation on a. c. stress waveforms.” in IEDM Tech. Dig., pp. 30-33, 1988.
7. J. Y. Choi, P. K. Ko, and C. Hu, “Hot-carrier-induced MOSFET degradation under ac stress,” IEEE Electron Device Lett., vol. EDL-8, no. 8, pp. 333-335, 1987.
8. Y. Igura and E. Takeda, “Hot-carrier degradation mechanism under ac stress in MOSFETs,” in Tech. Dig. 1987 S\mp. on VLSI Technology, pp. 47-48. 1987.
9. W. Weber. C. Werner, and G. Dorda, “Degradation of n-MOS-transistors after pulsed stress,” IEEE Electron Device Lett., vol. EDL-5, no. 12, pp. 518-520, 1984.
10. Y. A. El Mansy and A. R. Boothroyd. “A simple-two-dimensional model for IGFET operation in the saturation region,” IEEE Trans. Electron Devices, vol. ED-24, no. 3, pp. 254-261, 1977.
11. M. P. Brassington and R. R. Razouk, “The relationship between gate bias and hot-carrier-induced instabilities in buried- and surface-channel PMOSFETs'.” IEEE Trans. Electron Devices, vol. 35. no. 3. pp. 320-324, 1988.
12. M. Koyanagi, A. G. Lewis, R. A. Martin, T. Huang, and J. Chen. “Hot electron induced punchthrough in submicron PMOSFETs.” in Extended Abstracts 18th Conf. on Solid State Devices and Materials. (Tokyo, Japan), pp. 475-478, 1986.
13. R. Bellens, P. Heremans. G. Groeseneken, and H. E. Maes, “Characterization and analysis of hot-carrier degradation in p-channel transistors using constant current stress experiments,” Solid State Devices, pp. 261-264, 1988.