SITAR—An Efficient 3-D Simulator for Optimization of Nonplanar Trench Structures

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 9, Issue 11, 1990, Pages 1184-1188

  Bergner, Wolfgang ^a   Kircher, Roland ^a  

^a SIEMENS AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER GRAPHICS - THREE DIMENSIONAL GRAPHICS; DATA STORAGE, SEMICONDUCTOR; MATHEMATICAL TECHNIQUES - BOUNDARY VALUE PROBLEMS; OPTIMIZATION;

DRAM CELL SIMULATION; NONPLANAR TRENCH STRUCTURES; SOFTWARE PACKAGE SITAR; TRENCH CAPACITORS;

SEMICONDUCTOR DEVICES, MOSFET;

EID: 0025510061     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.62755     Document Type: Article

References (4)

1. D. M. Caughey and R. F. Thomas, “Carrier mobility in silicon empirically related to doping and field,” Proc. IEEE, vol. 54, p. 2192, 1967.
2. K. Yamaguchi, “A mobility model for carriers in the MOS inversion layer,” IEEE Trans. Electron Devices, vol. ED-30, p. 658, 1983.
3. J. W. Slotboom, “The pn-Product in silicon,” Solid-State Electron., vol. 20, p. 279, 1977.
4. W. Bergner, “Physikalische simulation von 3-d punch through effekter in der trenchzelle,” Master's thesis (in German), TU München, 1988.