The olympus synthesis system

IEEE Design and Test of Computers

Volumn 7, Issue 5, 1990, Pages 37-53

  De Micheli, Giovanni ^a   Ku, David ^a   Mailhot, Frédéric ^a   Truong, Thomas ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, DIGITAL - DESIGN; LOGIC CIRCUITS - DESIGN;

APPLICATION SPECIFIC INTEGRATED CIRCUITS (ASIC); OLYMPUS SYNTHESIS SYSTEM;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 0025505443     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.60605     Document Type: Article

References (12)

1. D. Ku and G. De Micheli, HardwareC: A Language for Hardware Design, tech. rpt. CSL-TR-90-419, Computer System Lab., Stanford Univ., Aug. 1990 (Version 2.0).
2. D. Ku and G. De Micheli, “High Level Synthesis and Optimization Strategies in Hercules and Hebe,” Proc. European ASIC Conf., 1990, pp. 124–129.
3. R. Brayton et al., “MIS: A Multiple-Level Logic Optimization System,” IEEE Trans. Computer-Aided Design, Vol. CAD-6, No. 6, Nov. 1987, pp. 1062–1081.
4. R. Camposano and W. Rosenstiel, “Synthesizing Circuits from Behavioral Descriptions,” IEEE Trans. Computer-Aided Design. Vol. CAD-8, No. 1, Feb. 1989, pp. 171–180.
5. M. McFarland, “Using Bottom-Up Design Techniques in the Synthesis of Digital Hardware from Abstract Behavioral Descriptions,” Proc. Design Automation Conf., 1986, pp. 474–480.
6. D. Ku and G. De Micheli, Relative Scheduling Under Timing Constraints, tech rpt. CSL-TR-89-401, Stanford University, Stanford, Calif., Nov. 1989; also in Proc. Design Automation Conf., 1990, pp. 59–64.
7. F. Mailhot and G. De Micheli, “Technology Mapping Using Boolean Matching and Don't Care Sets,” Proc. European Design Automation Conf., Mar. 1990, pp. 212–216.
8. K. Keutzer, “Technology Binding and Local Optimization by DAG Matching,” Proc. Design Automation Conf., 1987, pp. 341–347.
9. V. Rampa and G. De Micheli, “Computer-Aided Synthesis of a Discrete Cosine Transform Chip,” Proc. Inf'l Symp. Circuits and Systems, 1989, pp. 220–225.
10. M. Ligthart et al. “Design of a Digital Audio Input Output Chip,” Proc. Custom Integrated Circuit Conf., 1989, pp. 15.1.1-15.1.6.
11. D. Kasle, “High Resolution Decoding Techniques and Single-Chip Decoders for Multi-Anode MicroChannel Arrays,” Proc. Int'l Soc. for Optical Eng., Vol. 1158, Aug. 1989, pp. 311–318.
12. F. Mailhot and G. De Micheli, “Automatic Layout and Optimization of Static CMOS Cells,” Proc. Infl Conf. Computer Design, 1988, pp. 180–185.