A 20-ns 4-Mb CMOS SRAM with Hierarchical Word Decoding Architecture

IEEE Journal of Solid-State Circuits

Volumn 25, Issue 5, 1990, Pages 1068-1074

  Hirose, Toshihiko ^a   Kuriyama, Hirotada ^a   Murakami, Shuji ^a   Yuzuriha, Kojiro ^a   Mukai, Takao ^a   Tsutsumi, Kazuhito ^a   Nishimura, Yasumasa ^a   Kohno, Yoshio ^a   Anami, Kenji ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE, DIGITAL - RANDOM ACCESS; DATA STORAGE, SEMICONDUCTOR - STORAGE DEVICES; INTEGRATED CIRCUITS, CMOS;

CMOS TECHNOLOGY; STATIC RANDOM ACCESS - MEMORY (SRAM);

SEMICONDUCTOR DEVICES, MOS;

EID: 0025502963     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.62126     Document Type: Article

References (14)

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