High-Rate Viterbi Processor: A Systolic Array Solution

IEEE Journal on Selected Areas in Communications

Volumn 8, Issue 8, 1990, Pages 1520-1534

  Fettweis, Gerhard ^a   Meyr, Heinrich ^a  

^a RWTH AACHEN UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SYSTEMS, DIGITAL--PARALLEL PROCESSING; MATHEMATICAL TECHNIQUES--ALGORITHMS;

HIGHLY PARALLEL ARCHITECTURES; LINEAR VECTOR RECURSION; SYSTOLIC ARRAYS; VITERBI ALGORITHM; VLSI DESIGN;

INTEGRATED CIRCUITS, VLSI;

EID: 0025502943     PISSN: 07338716     EISSN: None     Source Type: Journal    
DOI: 10.1109/49.62830     Document Type: Article

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