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Volumn 11, Issue 8, 1990, Pages 336-338

The Implementation of a Reduced-Field Profile Design for High-Performance Bipolar Transistors

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR DEVICES - DESIGN;

EID: 0025477978     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.57926     Document Type: Article
Times cited : (23)

References (13)
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  • 3
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    • K. Sakui et al., “A new static memory cell based on the reverse base current effect of bipolar transistors,” IEEE Trans. Electron Devices, vol. 36, p. 1215, June 1989.
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    • Sakui, K.1
  • 4
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    • H. Ishiuchi, N. Tamba, J. D. Shott, C. J. Knorr, and S. S. Wong, “Hot-electron-induced minority carrier generation in bipolar junction transistors,” in 1989 IEDM Tech. Dig., pp. 803–806.
    • (1989) IEDM Tech. Dig. , pp. 803-806
    • Ishiuchi, H.1    Tamba, N.2    Shott, J.D.3    Knorr, C.J.4    Wong, S.S.5
  • 5
    • 0024611752 scopus 로고
    • A reduced-field design concept for high-performance bipolar transistors
    • D. D. Tang and P.-F. Lu, “A reduced-field design concept for high-performance bipolar transistors,” IEEE Electron Device Lett., vol. 10, no. 2, p. 67, 1989.
    • (1989) IEEE Electron Device Lett. , vol.10 , Issue.2 , pp. 67
    • Tang, D.D.1    Lu, P.-F.2
  • 6
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    • J. M. Early, “p-n-i-p and n-p-i-n junction transistor triodes,” Bell Syst. Tech. J., vol. 33, p. 517, 1954.
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  • 7
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    • A 20-pS Si bipolar IC using advanced self-aligned process technology with collector ion implantation
    • July
    • S. Konaka, E. Yamamoto, K. Sakuma, Y. Amemiya, and T. Sadai, “A 20-pS Si bipolar IC using advanced self-aligned process technology with collector ion implantation,” IEEE Trans. Electron Devices, vol. 36, p. 1370, July 1989.
    • (1989) IEEE Trans. Electron Devices , vol.36 , pp. 1370
    • Konaka, S.1    Yamamoto, E.2    Sakuma, K.3    Amemiya, Y.4    Sadai, T.5
  • 8
    • 5844399719 scopus 로고
    • Low-temperature silicon epitaxy by ultrahigh vaccum/chemical vapor deposition
    • Mar.
    • B. S. Meyerson, “Low-temperature silicon epitaxy by ultrahigh vaccum/chemical vapor deposition,” Appl. Phys. Lett., vol. 48, pp. 797–799, Mar. 1986.
    • (1986) Appl. Phys. Lett. , vol.48 , pp. 797-799
    • Meyerson, B.S.1
  • 9
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    • A 26 ps self-aligned epitaxial silicon base bipolar technology
    • to be presented at the
    • J. H. Comfort et al., “A 26 ps self-aligned epitaxial silicon base bipolar technology,” to be presented at the 1990 VLSI Symp.
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  • 10
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    • Collector signal delay in the presence of velocity overshoot
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  • 11
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    • A general control-volume formulation for modeling impact ionization in semiconductor transport
    • Oct.
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  • 13
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.