Scaling of Digital BiCMOS Circuits

IEEE Journal of Solid-State Circuits

Volumn 25, Issue 4, 1990, Pages 932-941

  Bellaouar, Abdellatif ^a   Embabi, Sherif H K ^a   Elmasry, Mohamed I ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC CIRCUITS, EMITTER COUPLED; TRANSISTORS, BIPOLAR;

BANDGAP NARROWING; BIPOLAR JUNCTION TRANSISTOR; CMOS/ECL CONVERTER; CONSTANT COLLECTOR CURRENT (CIC); DIGITAL BICMOS CIRCUITS SCALING; ECL/CMOS CONVERTER;

INTEGRATED CIRCUITS, DIGITAL;

EID: 0025474623     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.58285     Document Type: Article

References (30)

1. M. Odaka et al., “A 512kb/5ns BiCMOS RAM with lkG/150ps logic gate array,” in ISSCC Dig. Tech. Papers, Feb. 1989, pp. 28–29.
2. H. Tran et al., “An 8ns BiCMOS 1Mb ECL SRAM with a configurable memory array size,” in ISSCC Dig. Tech. Papers, Feb. 1989, pp. 36–37.
3. M. Matsui et al., “An 8ns 1Mb ECL BiCMOS SRAM,” in ISSCC Dig. Tech. Papers, Feb. 1989, pp. 38–39.
4. H. Fukuda et al., “A BiCMOS channelless masterslice with on-chip voltage converter,” in ISSCC Dig. Tech. Papers, Feb. 1989, pp. 176–177.
5. T. Hotta et al., “A 70MHz-32b microprocessor with 1.0 µm BiCMOS macrocell library,” in ISSCC Dig. Tech. Papers, Feb. 1989, pp. 124–125.
6. T. Hotta et al., “1.3 um CMOS/bipolar macrocell library for VLSI computer,” IEEE J. Solid-State Circuits, vol. 23, no. 2, pp. 500–506, Apr. 1988.
7. H. Higuchi et al., “Performance and structures of scaled-down bipolar devices merged with CMOSFETs,” in IEDM Tech. Dig., Dec. 1984, pp. 694–697.
8. A. Watanabe et al., “Proposal of high speed bipolar-CMOS merged VLSI technology,” Electron. Commun. Japan, vol. 71, no. 6, pt. 2, pp. 63–73, 1988.
9. H. Momose et al., “0.5 micron BiCMOS technology,” in IEDM Tech. Dig., Dec. 1987, pp. 838–840.
10. T. Yamaguchi and T. H. Yuzuriha, “Process integration and device performance of a submicrometer BiCMOS with 16-GHz f1 double poly-bipolar devices,” IEEE Trans. Electron Devices, vol. 36, no. 5, pp. 890–896, May 1989.
11. K-Y. Toh, “An engineering model for short-channel MOS devices,” IEEE J. Solid-State Circuits, vol. 23, no. 4, pp. 950–958, Aug. 1988.
12. R. H. Dennard et al., “Design of ion implanted MOSFETs with very small physical dimensions,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 256–266, Oct. 1974.
13. P. K. Chatterjee et al., “The impact of scaling laws on the choice of n-channel or p-channel for MOS VLSI,” IEEE Electron Device Lett., vol. EDL-1, pp. 220–223, Oct. 1980.
14. J. R. Brews et al., “Generalized guide for MOSFET miniaturization,” IEEE Electron Device Lett., vol. EDL-1, pp. 2–4, Jan. 1980.
15. G. Baccarani et al., “Generalized scaling theory and its application to a 1/4 micrometer MOSFET design,” IEEE Trans. Electron Devices, vol. ED-31, no. 4, pp. 452–462, Apr. 1984.
16. P. M. Solomon and D. D. Tang, “Bipolar circuit scaling,” in ISSCC Dig. Tech. Papers, Feb. 1979, pp. 86–87.
17. T. H. Ning et al., “Scaling properties of bipolar devices,” in IEDM Tech. Dig., Dec. 1980, pp. 61–64.
18. N. Hanaoka and A. Anzai, “Perspective of scaled bipolar devices,” in IEDM Tech. Dig., Dec. 1981, pp. 512–515.
19. T. H. Ning, “Materials and physics issues in scaling bipolar devices,” J. Vac. Sci. Technol. A, vol. 5, no. 4, pp. 1394–1395, July/Aug. 1987.
20. D. D-L. Tang et al., “Junction degradation in bipolar transistors and the reliability imposed constraints to scaling and design,” IEEE Trans. Electron Devices, vol. 35, no. 12, pp. 2101–2107, Dec. 1988.
21. A. Bellaouar, S. Embabi, and M. I. Elmasry, “Scaling of digital BiCMOS circuit structures,” in IEDM Tech. Dig., Dec. 1989, pp. 437–440.
22. C. L. Williams et al., “Optimization and temperature dependance of current gain in polysilicon-emitter-contacted bipolar transistors,” in BCTM Tech. Dig., Sept. 1988, pp. 50–54.
23. Y. Nishio et al., “A BiCMOS logic gate with positive feedback,” in ISSCC Dig. Tech. Papers, Feb. 1989, pp. 116–117.
24. S. Embabi, A. Bellaouar, and M. I. Elmasry, “Analysis and optimization of BiCMOS digital circuit structures,” submitted to IEEE J. Solid-State Circuits, 1989.
25. S. M. Sze, Physics of Semiconductor Devices. New York; Wiley, 1981.
26. T. H. Ning and R. D. Isaac, “Effect of emitter contact on current gain of silicon bipolar devices,” IEEE Trans. Electron Devices, vol. ED-27, pp. 2051–2055, Nov. 1980.
27. B. Soerowirdjoeral, “The influence of surface treatment on the electrical characteristics of poly-emitter bipolar transistors,” in IEDM Tech. Dig., Dec. 1982, pp. 668–671.
28. J-C. S. Woo and J. D. Plummer, “Optimization of silicon bipolar transistors for high current gain at low temperatures,” IEEE Trans. Electron Devices, vol. 35, no. 8, pp. 1311–1321, Aug. 1988.
29. D. Arora, J. R. Hauser, and D. J. Roulston, “Electron and hole mobilities in silicon as a function of concentration and temperature,” IEEE Trans. Electron Devices, vol. ED-29, pp. 284–291, Feb. 1982.
30. M.-C. Jeng et al., “Design guidelines for deep-submicrometer MOSFETs,” in IEDM Tech. Dig., Dec. 1988, pp. 386–389.