Power-Supply Voltage Impact on Circuit Performance for Half and Lower Submicrometer CMOS LSI

IEEE Transactions on Electron Devices

Volumn 37, Issue 8, 1990, Pages 1902-1908

  Kakumu, Masakazu ^a,b   Kinugawa, Masaakl ^b  

^a HEWLETT PACKARD COMPANY   (United States)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC FIELD EFFECTS; ELECTRONIC CIRCUITS, POWER SUPPLY; SEMICONDUCTOR DEVICES, MOS; SEMICONDUCTOR DEVICES, MOSFET;

CRITICAL ELECTRIC FIELD; MOS DEVICE SCALING; SUBMICROMETER CMOS LSI; TRANSCONDUCTANCE BEHAVIOR;

INTEGRATED CIRCUITS, LSI;

EID: 0025474203     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.57142     Document Type: Article

References (22)

1. R. H. Dennard, F. H. Gaensslen, H.-N. Yu, V. L. Rideout, E. Bassons, and A. R. Leblank, “Design of ion implanted MOSFET’s with very small physical dimensions,” IEEE. J. Solid-Stute Circuits, vol. SC-9, pp. 256–268, Oct. 1974.
2. P. K. Chatterjee, W. R. Hunter, T. C. Holloway, and Y. T. Lin, “The impact of scaling laws on the choice of n-channel and p-channel fir MOS VLSI,” IEEE Electron Device Lett., vol. EDL-1, pp. 220–223, Oct. 1980.
3. G. Bacarrani, M. R. Wordeman, and R. H. Dennard, “Generalized scaling theory in its application to a 1/4 micrometer MOS design,” IEEE Trans. Electron Devices, vol. ED-31, pp. 452–462, Apr. 1984.
4. L. K. Wang, Y. Taur, D. Moy, R. H. Dennard, K. Cjiong, F. Hohn, and P. J. Coane, “0.5 micron gate CMOS technology using e-beam/optical mix lithography,” in Proc. VLSI Symp. 1987, pp. 13–14.
5. L. K. Wang, C. H. Hsu, D. Seeger, J. S. Silverman, D. Zicherman, C. K. Hu, R. Acosta, R. Vismanathan, J. Warlaumont, and A. Wilson. “0.5 µn CMOS devices and circuit fabricated using synchrotron X-ray lithography,” in Proc. VLSI Symp. 1989, pp. 11–12.
6. Y. Okazaki, T. Kobayashi, M. Miyake, T. Matsuda, K. Sakuma, Y. Kawai, and M. Takahashi, “A high performance 0.22 µm CMOS technology,” in Proc. VLSI Symp. 1989, pp. 13–14.
7. B. Davari, W. H. Chang, M. R. Wordeman, C. S. Oh, Y. Taur, K. Epetrillo, D. Moy, J. J. Bucchigano, H. T. Ng, M. G. Rosenfields, F. J. Hohn, and M. D. Rodriguez, “A high performance 0.25 µm CMOS technology,” in IEDM Tech. Dig., pp. 56–60, 1988.
8. G. A. Sai-Halasz, M. R. Wordeman, D. P. Kern, S. Rishton, E. Ganin, H. Y. Ng, D. Moy, T. H. P. Chang, and R. H. Dennard. “Inverter performance of deep-submicrometer MOSFET’s.” IEEE Electron Device Lett., vol. 9, pp. 633–635, Dec. 1988.
9. N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design. New York, NY: Addison-Wesley, 1985, p. 137.
10. D. C. Mayer and W. E. Perkins, “Analysis of the switching of a submicrometer-gate CMOS/SOS inverter,” IEEE Trans. Electron Devices, vol. ED-28, pp. 886-888, July 1981.
11. M. Shoji, CMOS Digital Circuit Technology. Englewood Cliffs, NJ: Prentice-Hall, 1988, p. 123.
12. C. G. Sodini, P. K. Ko, and J. L. Moll, “The effect of high fields on MOS device and circuit performance devices,” IEEE Trans. Electron Devices, vol. ED-31, pp. 1386–1393, Oct. 1984.
13. M. Kakumu, M. Kinugawa. and K. Hashimoto, “Choice of power supply voltage for half and submicrometer CMOS devices,” IEEE Trans. Electron Devices, vol. 37, no. 5. pp. 1334–1342, May 1990.
14. J. S. T. Huang, “MOS/bipolar technology trade-offs for VLSI,” in VLSI Microelectronics, N. G. Einspuch, ed. Orlando, FL: Academic Press, 1985, ch. 9, pp. 21–35.
15. J. A. Cooper, Jr. and D. F. Nelson, “High-field drift velocity of electrons at Si/SiO2 interface as determined by a time-of-fiight technique,” J. Appt. Phys., vol. 54, pp. 1445–1456, 1983.
16. D. F. Nelson, J. A. Cooper, Jr., and A. R. Tetola, “High-field drift velocity of holes in inversion layers on silicon,” Appt. Phys. Lett., vol. 41, pp. 857–860, 1982.
17. R. W. Coen and R. S. Muller, “Velocity surface carriers in inversion layers on silicon,” Solid-State Electron., vol. 23, pp. 35–40, 1980.
18. M. Matusi, Y. Urakawa, K. Ochii, T. Sakurai, and T. lizuka, “Access-time scaling of CMOS and Bi-CMOS SRAMs,” in Denshi-Jouhou Tsushingakkai, pp. 5–292, 1989 (in Japanese).
19. K. Ochii, K. Hashimoto, H. Yasuda, M. Masuda. H. Nozawa, and S. Kohyama, “A 15 nW standby power 64 kb CMOS SRAM,” in ISSCC Dig. Tech. Papers, pp. 260–261, Feb. 1982.
20. T. Sakurai, K. Sawada, K. Nogami, T. Wada, M. Isobe, M. Kakumu, S. Morita, S. Yokogawa, M. Kinugawa, T. Asami, K. Hashimoto, J. Matsunaga, H. Nozawa, and T. lizuka, “A 1 Mb virtually SRAM,” in ISSCC Dig. Tech. Papers, pp. 252–253, Feb. 1985.
21. T. Ohtani, K. Hashimoto, M. Matsui, J. Tsujimoto, H. Iwai, M. Saitoh, H. Shibata, H. Sasaki, M. Isobe, J. Matsunaga, and T. lizuka, “A 25 ns 1 Mb CMOS SRAM,” in ISSCC Dig. Tech. Papers, pp. 264–265, Feb. 1987.
22. M. Kakumu, M. Kinugawa, S. Morita, T. Nakayama, T. Asami, T. Yoshida, K. Ochii, and J. Matsunaga, “0.5 µ gate 1 M SRAM with high performance at 3.3 V,” in Proc. VLSI Symp. 1989, pp. 63–64.