On the robustness of LDD nMOS transistors subjected to measurement of drain breakdown voltage

Solid State Electronics

Volumn 33, Issue 8, 1990, Pages 1043-1048

  Aur, Shian ^a   Chatterjee, Amitava ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC MEASUREMENTS--VOLTAGE; SEMICONDUCTOR DEVICES, MOSFET; SUBSTRATES;

DRAIN BREAKDOWN VOLTAGE; LDD NMOS TRANSISTORS; LIGHTLY DOPED DRAIN (LDD) MOSFET'S; ROBUSTNESS; SUBSTRATE RESISTANCE MEASUREMENT; SUBTHRESHOLD CURRENT;

TRANSISTORS;

EID: 0025472187     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/0038-1101(90)90218-4     Document Type: Article

References (12)

1. A numerical model of avalanche breakdown in MOSFET's