Layout Optimization of Static CMOS Functional Cells

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 9, Issue 7, 1990, Pages 708-719

  Maziasz, Robert L ^a,b   Hayes, John P ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

^b Applied Dynamics International ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, CMOS; LOGIC DEVICES--GATES; SEMICONDUCTOR DEVICES, MOS--COMPUTER AIDED DESIGN;

MINIMUM-AREA LAYOUTS;

INTEGRATED CIRCUITS, DIGITAL;

EID: 0025464139     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.55210     Document Type: Article

References (17)

1. W. Bridgewater and R. Pokala, “Cell synthesis for ASICs,” in Proc. Custom Integrated Circuits Conf., 1987, pp. 371–374.
2. C. Y. R. Chen and C. Y. Hou, “A new layout optimization methodology for CMOS complex gates,” in Proc. Int. Conf. on Computer-Aided Design, Nov. 1988, pp. 368–371.
3. F. Harary, Graph Theory. Reading, MA: Addison-Wesley, 1969.
4. M. A. Harrison, Introduction to Switching and Automata Theory. New York: McGraw-Hill, 1965.
5. H. Heeb and W. Fichtner, “GRAPES: A module generator based on graph planarity,” in Proc. Int. Conf. on Computer-Aided Design, Nov. 1987, pp. 428–431.
6. D. Hill, “Sc2: A hybrid automatic layout system,” in Proc. Int. Conf. on Computer-Aided Design, Nov. 1985, pp. 172–174.
7. Y. M. Huang and M. Sarrafzadeh, “Parallel algorithms for minimum dual-cover with application to CMOS layout,” in Proc. Int. Conf. on Parallel Processing, Aug. 1988, pp. 26–33.
8. T. Lengauer and R. Müller, “Linear algorithms for optimizing the layout of dynamic CMOS cells,” IEEE Trans. Circuits Syst., vol. 35, pp. 279–285, Mar. 1988.
9. F. Mailhot and G. DeMicheli, “Automatic layout and optimization of static CMOS cells,” in Proc. Int. Conf. on Computer Design, Oct. 1988, pp. 180–185.
10. T. Mano et al., “OCCAM to CMOS,” in Computer Hardware Description Languages and Their Applications, C. J. Koomen and T. Moto-oka, eds. Amsterdam, The Netherlands: North-Holland, 1985, pp. 381–390.
11. R. L. Maziasz and J. P. Hayes, “Layout optimization of CMOS functional cells,” in Proc. 24th Design Automation Conf., July 1987, pp. 77–84.
12. H. Miyashita et al., “An automatic cell pattern generation system for CMOS transistor-pair array LSI,” Integration, vol. 4, pp. 115–133, 1986.
13. R. Nair, A. Brass and J. Reif, “Linear-time algorithms for optimal CMOS layout,” in VLSI: Algorithms and Architectures, P. Bertolazzi and F. Luccio, eds. Amsterdam, The Netherlands: North-Holland, 1985, pp. 327–338.
14. T. Takamizawa et al., “Linear-time computability of combinatorial problems on series-parallel graphs,” J. Ass. Comput. Mach., vol. 29, no. 3, pp. 623–641, July 1982.
15. T. Uehara and W. M. vanCleemput, “Optimal layout of CMOS functional arrays,” IEEE Trans. Comput., vol. C-30, pp. 305–312, May 1981.
16. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design. Reading, MA: Addison-Wesley, 1985.
17. S. Wimer et al., “Optimal chaining of CMOS transistors in a functional cell,” IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 795–801, Sept. 1987.