Parameter Correlation and Modeling of the Power-Law Relationship in MOSFET Hot-Carrier Degradation

IEEE Electron Device Letters

Volumn 11, Issue 7, 1990, Pages 297-299

  Sun, Shih Wei ^a   Orlowski, Marius ^a   Fu, Kuan Yu ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR MATERIALS--HOT CARRIERS; TRANSISTORS, FIELD EFFECT--DEGRADATION;

SUBMICROMETER PROCESSING TECHNOLOGIES;

SEMICONDUCTOR DEVICES, MOSFET;

EID: 0025462473     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.56480     Document Type: Article

References (11)

1. E. Takeda and N. Suzuki, “An empirical model for device degradation due to hot-carrier injection,” IEEE Electron Device Lett., vol. EDL-4, no. 4, pp. 111–113, 1983.
2. C. Hu et al., “Hot-electron-induced MOSFET degradation-Model, monitor, and improvement,” IEEE Trans. Electron Devices, vol. ED-32, no. 2, pp. 375–385, 1985.
3. P. Heremans, R. Bellens, G. Groeseneken, and H. E. Maes, “Consistent model for the hot-carrier degradation in n-channel and p-channel MOSFET's,” IEEE Trans. Electron Devices, vol. 35, no. 12, pp. 2194–2209, 1988.
4. K. M. Cham, J. Hui, P. V. Voorde, and H. S. Fu, “Self-limiting behavior of hot carrier degradation and its implication on the validity of lifetime extraction by accelerated stress,” in Proc. IEEE Int. Reliability Phys. Symp., 1987, pp. 191–194.
5. S. W. Sun et al., “A dual-poly (nβ/pβ) gate, Ti-salicide, double-metal technology for submicron CMOS ASIC and logic applications,” in Proc. IEEE Custom Integrated Circuit Conf., 1989, pp. 18.7.1–4.
6. I.-C. Chen, C. C. Wei, and C. W. Teng, “Simple gate-to-drain overlapped MOSFET's using poly spacers for high immunity to channel hot-electron degradation,” IEEE Electron Device Lett., vol. 11, no. 2, pp. 78–81, 1990.
7. S. Aur, “Kinetics of hot carrier effects for circuit simulation,” in Proc. IEEE Int. Reliability Phys. Symp., 1989, pp. 88–91.
8. M. R. Trocino, K.-Y. Fu, and K. W. Teng, “Stress-bias dependence of hot-carrier-induced degradation in MOSFETs,” Solid-State Electron., vol. 31, no. 5, pp. 873–875, 1988.
9. M.-L. Chen et al., “Suppression of hot-carrier effects in submicrome-ter CMOS technology,” IEEE Trans. Electron Devices, vol. 35, no. 12, pp. 2210–2220, 1988.
10. M. Koyanagi, A. G. Lewis, R. A. Martin, T.-Y. Huang, and J. Y. Chen, “Hot-electron-induced punchthrough (HEIP) effect in submi-cron PMOSFET's,” IEEE Trans. Electron Devices, vol. ED-34, no. 4, pp. 839–844, 1987.
11. J. J. Tzou, C. C. Yao, R. Cheung, and H. W. K. Chan, “Hot-carrier-induced degradation in p-channel MOSFET's,” IEEE Electron Device Lett., vol. EDL-7, no. 1, pp. 5–7, 1986.