An MOS Four-Quadrant Analog Multiplier Using Simple Two-Input Squaring Circuits with Source Followers

IEEE Journal of Solid-State Circuits

Volumn 25, Issue 3, 1990, Pages 841-848

  Song, Ho Jun ^a   Kim, Choong Ki ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR DEVICES, MOS; SIGNAL DISTORTION;

HARMONIC DISTORTION; METAL GATE NMOS PROCESS; MOS FOUR-QUADRANT ANALOG MULTIPLIER; SOURCE FOLLOWERS; SQUARING CIRCUITS; SUBSTRATE BIAS EFFECT;

COMPUTERS, ANALOG;

EID: 0025448598     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.102683     Document Type: Article

References (16)

1. J. N. Babanezhad and G. C. Temes, “A 20-V four-quadrant CMOS analog multiplier,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 1158–1168, Dec. 1985.
2. D. C. Soo and R. G. Meyer, “A four-quadrant NMOS analog multiplier,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 1174–1178, Dec. 1982.
3. S.-C. Qin and R. L. Gieger, “A ±5V CMOS analog multiplier,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 1143–1146, Dec. 1987.
4. J. S. Pena-Finol and J. A. Connelly, “A MOS four-quadrant analog multiplier using the quarter-square technique,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 1064–1073, Dec. 1987.
5. K. Bult and H. Wallinga, “A CMOS four-quadrant analog multiplier,” IEEE J. Solid-State Circuits, vol. SC-21, pp. 430–435, June 1986.
6. D. Brodarac et al., “Novel sampled-data MOS multiplier,” Electron. Lett., vol. 18, 229–230, 1982.
7. B. Gilbert, “A precision four-quadrant multiplier with nanosecond response,” IEEE J. Solid-State Circuits, vol. SC-3, pp. 353–365, Dec. 1968.
8. B. S. Song, “CMOS RF circuits for data communication application,” IEEE J. Solid-State Circuits, vol. SC-21, pp. 310–317, Apr. 1986.
9. Z. Hong and H. Melchior, “Four-quadrant CMOS analog multiplier” Electron. Lett., vol. 20, 1015–1016, Nov. 1984.
10. B. Gilbert, “A high-performance monolithic multiplier,” IEEE J. Solid-State Circuits, vol. SC-9, 364–373, Dec. 1974.
11. M. Banu and Y. P. Tsividis, “Floating voltage-controlled resistor in CMOS technology,” Electron. Lett., vol. 18, pp. 678–679, July 1982.
12. J. N. Babanezhad and G. C. Temes, “Linear MOS simulated resistors,” in Proc. IEEE Int. Circuits 1985.
13. S. Wong and C. A. Salama, “Impact of scaling on MOS analog performance,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 106–114, Feb. 1983.
14. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 2nd ed. New York: Wiley, 1984, pp. 593–605.
15. R. S. Muller and T. I, Kamins, Device Electronics for Integrated Circuits. New York: Wiley, 1977, pp. 352–354.
16. Y. P. Tsividis, “Design consideration in single-channel MOS analog integrated circuits—A tutorial,” IEEE J. Solid-State Circuits, vol. SC-13, pp. 383–391, June 1978.