Artificial Neural Networks Using MOS Analog Multipliers

IEEE Journal of Solid-State Circuits

Volumn 25, Issue 3, 1990, Pages 849-855

  Hollis, Paul W ^a   Paulos, John J ^a  

^a NORTH CAROLINA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS, ANALOG--MULTIPLYING CIRCUITS; INTEGRATED CIRCUITS, VLSI;

ANALOG MULTIPLIER NEURON; COMMON MODE BIASING; DIFFERENTIAL NEURON SIGNALS; GRAPH PARTITIONING PROBLEMS; HOPFIELD NETWORKS; MOS ANALOG MULTIPLIERS;

NEURAL NETWORKS;

EID: 0025445432     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.102684     Document Type: Article

References (19)

1. J. J. Hopfield and D. W. Tank, “Neural computations of decisions in optimization problems,” Biol. Cybern., vol. 52, pp. 141–152, 1985.
2. J. J. Hopfield, “Neural networks and physical systems with emergent collective computational abilities,” Proc. Nat. Acad. Sci. USA, vol. 79, 2554–2558, 1982.
3. M. F. Tenorio and C. S. Hughes, “Real time noisy image segmentation using an artificial neural network model,” in Proc. IEEE 1st Int. Conf. Neural Networks, vol. IV, 1987, pp. 357–365.
4. H. P. Graf and P. deVegvar, “A CMOS implementation of a neural network model,” in Proc. 1987 Stanford Conf.: Advanced Res. VLSI, 1987, pp. 351–367.
5. M. A. Sivilotti, M. R. Emerling, and C. A. Mead, “VLSI architecture for implementation of neural networks,” in Amer. Inst. Phys. Conf. Proc., vol. 151, 1986, pp. 408–413.
6. J. Alspector and R. B. Allen, “A neuromorphic VLSI learning system,” in Proc. 1987 Stanford Conf.: Advanced Res. VLSI, 1987, pp. 313–349.
7. H. P. Graf et al., “VLSI implementation of a neural network memory with several hundreds of neurons,” in Amer. Inst. Phys. Conf. Proc., vol. 151, 1986, pp. 182–187.
8. C. A. Mead, Analog VLSI and Neural Systems. Reading, MA: Addison-Wesley, 1989, ch. 7.
9. S. Eberhardt, T. Duong, and A. Thakoor, “Design of parallel hardware neural network systems from custom VLSI ‘building block’ chips,” in Proc. Int. Joint Conf. Neural Networks, vol. II, 1989, p. 183.
10. F. Kub, K. Moon, Andai I. Mack, “Cascadable 32×32 vector-matrix multiplier for artificial neural networks,” presented at the Int. Joint Conf. Neural Networks, 1989.
11. M. Holler, S. Tam, H. Castro, and R. Benson, “An electrically trainable artificial neural network (ETANN) with 10240 ‘floating gate’ synapses,” in Proc. Int. Joint Conf. Neural Networks, vol. II. 1989, p. 191.
12. J. Paulos and P. Hollis, “Artificial neural networks using MOS analog multipliers,” presented at Int. Symp. Circuits and Systems, 1988.
13. P. Hollis and J. Paulos, “Neural networks using analog multipliers,” presented at the Int. Conf. Neural Networks, 1988.
14. G. E. Hinton, “Boltzmann machines: Constraint satisfaction networks that learn,” Carnegie Mellon Univ., Pittsburgh, PA, Tech. Rep. CMU-CS-84-119, 1984.
15. D. E. Van den Bout and T. K. Miller III, “Graph partitioning using annealed neural networks,” in Proc. Int. Joint Conf. Neural Networks, vol. I, 1989, p. 521.
16. G. C. Fox and W. Furmanski, “Load balancing by a neural network,” in Proc. 3rd Hypercube Conf., 1988, pp. 241–277.
17. J. Rafel, J. Mann, R. Berger, A. Soares, and S. Gilbert, “A generic architecture for wafer-scale neuromorphic systems,” in Proc. IEEE 1st Int. Conf. Neural Networks, vol. III, 1987, p. 501.
18. P. Hollis and J. Paulos, “The effects of precision constraints in a back-propagation learning network,” presented at the Int. Joint Conf. Neural Networks, 1989.
19. D. Bisset and P. Daniell, “Steps toward a VLSI implementation of the back propagation algorithm: Non-linear synaptic functions,” presented at the Int. Joint Conf. Neural Networks, 1989.