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1
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0023010072
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Advanced techniques for concurrent multilevel simulation
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presented at the ICCAD, Santa Clara, CA
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S. Gai, F. Somenzi, and E. Ulrich, “Advanced techniques for concurrent multilevel simulation,” presented at the ICCAD, Santa Clara, CA, 1986.
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(1986)
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Gai, S.1
Somenzi, F.2
Ulrich, E.3
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2
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84939355520
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Advances in concurrent multilevel simulation
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—, “Advances in concurrent multilevel simulation,” IEEE Trans. on Computer-Aided Design, vol. CAD-6, pp. 1006–1012, 1987.
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(1987)
IEEE Trans. on Computer-Aided Design
, vol.CAD-6
, pp. 1006-1012
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3
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0021554098
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DECSIM: A Multi-level simulation system for digital design
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presented at the ICCD, Port Chester, NY
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M. A. Kearney, “DECSIM: A Multi-level simulation system for digital design,” presented at the ICCD, Port Chester, NY, 1984.
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(1984)
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Kearney, M.A.1
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4
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84935249987
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M.A. thesis, Worcester Polytechnic Institute, Worcester, MA
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D. J. Machlin, “A general purpose traversal mechanism for concurrent logic simulation,” M.A. thesis, Worcester Polytechnic Institute, Worcester, MA, 1987.
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(1987)
A general purpose traversal mechanism for concurrent logic simulation
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Machlin, D.J.1
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5
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0024123369
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Switch-Level concurrent fault simulation based on general purpose list traversal mechanism
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Washington, DC
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D. J. Machlin, D. Gross, S. Kadkade, and E. Ulrich, “Switch-Level concurrent fault simulation based on general purpose list traversal mechanism,” in Proc. IEEE Int. Test Conf., Washington, DC, 1988, pp. 574–581.
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(1988)
Proc. IEEE Int. Test Conf.
, pp. 574-581
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Machlin, D.J.1
Gross, D.2
Kadkade, S.3
Ulrich, E.4
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6
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84941502574
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Speed and accuracy in digital networks based on structural modeling
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presented at the DAC, Las Vegas
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E. Ulrich and D. Hebert, “Speed and accuracy in digital networks based on structural modeling,” presented at the DAC, Las Vegas, 1982.
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(1982)
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Ulrich, E.1
Hebert, D.2
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7
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0022298351
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Concurrent simulation at the switch, gate, and register levels
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presented at the IEEE Int. Test Conf., Philadephia, PA
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E. Ulrich, “Concurrent simulation at the switch, gate, and register levels,” presented at the IEEE Int. Test Conf., Philadephia, PA, 1985.
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(1985)
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Ulrich, E.1
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8
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0020901069
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Design verification for very large networks based on concurrent simulation and clock suppression
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presented at the ICCD, Port Chester, NV
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E. Ulrich, M. Kearney, J. Tellier, and S. Demba, “Design verification for very large networks based on concurrent simulation and clock suppression, presented at the ICCD, Port Chester, NV, 1983.
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(1983)
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Ulrich, E.1
Kearney, M.2
Tellier, J.3
Demba, S.4
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10
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84941489364
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Fault simulation in the development of a VAX CPU microdiagnostic package
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presented at the DEC Internal Test Sym., Oct.
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G. McCarthy, “Fault simulation in the development of a VAX CPU microdiagnostic package,” presented at the DEC Internal Test Sym., Oct. 1987.
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(1987)
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McCarthy, G.1
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