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Volumn 9, Issue 6, 1990, Pages 621-628

Experiences with Concurrent Fault Simulation of Diagnostic Programs

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION--APPLICATIONS; DATA STORAGE, SEMICONDUCTOR--STORAGE DEVICES; STATISTICAL METHODS--APPLICATIONS;

EID: 0025442670     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.55192     Document Type: Article
Times cited : (1)

References (10)
  • 1
    • 0023010072 scopus 로고
    • Advanced techniques for concurrent multilevel simulation
    • presented at the ICCAD, Santa Clara, CA
    • S. Gai, F. Somenzi, and E. Ulrich, “Advanced techniques for concurrent multilevel simulation,” presented at the ICCAD, Santa Clara, CA, 1986.
    • (1986)
    • Gai, S.1    Somenzi, F.2    Ulrich, E.3
  • 2
    • 84939355520 scopus 로고
    • Advances in concurrent multilevel simulation
    • —, “Advances in concurrent multilevel simulation,” IEEE Trans. on Computer-Aided Design, vol. CAD-6, pp. 1006–1012, 1987.
    • (1987) IEEE Trans. on Computer-Aided Design , vol.CAD-6 , pp. 1006-1012
  • 3
    • 0021554098 scopus 로고
    • DECSIM: A Multi-level simulation system for digital design
    • presented at the ICCD, Port Chester, NY
    • M. A. Kearney, “DECSIM: A Multi-level simulation system for digital design,” presented at the ICCD, Port Chester, NY, 1984.
    • (1984)
    • Kearney, M.A.1
  • 5
    • 0024123369 scopus 로고
    • Switch-Level concurrent fault simulation based on general purpose list traversal mechanism
    • Washington, DC
    • D. J. Machlin, D. Gross, S. Kadkade, and E. Ulrich, “Switch-Level concurrent fault simulation based on general purpose list traversal mechanism,” in Proc. IEEE Int. Test Conf., Washington, DC, 1988, pp. 574–581.
    • (1988) Proc. IEEE Int. Test Conf. , pp. 574-581
    • Machlin, D.J.1    Gross, D.2    Kadkade, S.3    Ulrich, E.4
  • 6
    • 84941502574 scopus 로고
    • Speed and accuracy in digital networks based on structural modeling
    • presented at the DAC, Las Vegas
    • E. Ulrich and D. Hebert, “Speed and accuracy in digital networks based on structural modeling,” presented at the DAC, Las Vegas, 1982.
    • (1982)
    • Ulrich, E.1    Hebert, D.2
  • 7
    • 0022298351 scopus 로고
    • Concurrent simulation at the switch, gate, and register levels
    • presented at the IEEE Int. Test Conf., Philadephia, PA
    • E. Ulrich, “Concurrent simulation at the switch, gate, and register levels,” presented at the IEEE Int. Test Conf., Philadephia, PA, 1985.
    • (1985)
    • Ulrich, E.1
  • 8
    • 0020901069 scopus 로고
    • Design verification for very large networks based on concurrent simulation and clock suppression
    • presented at the ICCD, Port Chester, NV
    • E. Ulrich, M. Kearney, J. Tellier, and S. Demba, “Design verification for very large networks based on concurrent simulation and clock suppression, presented at the ICCD, Port Chester, NV, 1983.
    • (1983)
    • Ulrich, E.1    Kearney, M.2    Tellier, J.3    Demba, S.4
  • 9
    • 84939343058 scopus 로고
    • Techniques for logic and fault simulation
    • E. Ulrich and I. Suetsugu, “Techniques for logic and fault simulation,” VLSI Syst. Design, 1986.
    • (1986) VLSI Syst. Design
    • Ulrich, E.1    Suetsugu, I.2
  • 10
    • 84941489364 scopus 로고
    • Fault simulation in the development of a VAX CPU microdiagnostic package
    • presented at the DEC Internal Test Sym., Oct.
    • G. McCarthy, “Fault simulation in the development of a VAX CPU microdiagnostic package,” presented at the DEC Internal Test Sym., Oct. 1987.
    • (1987)
    • McCarthy, G.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.