Estimation of Maximum Currents in MOS IC Logic Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 9, Issue 6, 1990, Pages 642-654

  Chowdhury, S ^a   Barkatullah, Javed Sabir ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC CIRCUITS--TESTING; SEMICONDUCTOR DEVICES, MOS--TESTING;

MOS IC LOGIC CIRCUITS; WAFER SCALE TECHNOLOGY;

INTEGRATED CIRCUITS, DIGITAL;

EID: 0025439702     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.55194     Document Type: Article

References (13)

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