The Multistable Charge-Controlled Memory Effect in SOI MOS Transistors at Low Temperatures

IEEE Transactions on Electron Devices

Volumn 37, Issue 5, 1990, Pages 1373-1382

  Tack, Marnix R ^a   Gao, Minghui ^a,b   Claeys, Cor L ^a   Declerck, Gilbert J ^a  

^a IMEC   (Belgium)

^b FUDAN UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR DEVICES, MOS;

CHARGE-CONTROLLED MEMORY EFFECT; MCCM (MULTISTABLE CHARGE-CONTROLLED MEMORY); MOS TRANSISTORS; SOI MOS TRANSISTORS;

TRANSISTORS, FIELD EFFECT;

EID: 0025433827     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.108200     Document Type: Article

References (14)

1. F. H. Gaensslen and R. C. Jaeger, “Temperature dependent threshold behavior of depletion mode MOSFET’s—Characterization and simulation,” Solid-State Electron., vol. 22, no. 4, pp. 423–430, Apr. 1979.
2. S. Hannamura, M. Aoki, T. Masuhara, O. Minato, Y. Sakai, and T. Hayashida, “Operation of bulk CMOS devices at very low temperatures,” IEEE J. Solid-State Circuits, vol. SC-21, no. 3, pp. 484–490, June 1986.
3. R. C. Jaeger and F. H. Gaensslen, “Low temperature MOS microelectronics,” in Proc. Symp. on Low Temperature Electronics and High Temperature Superconductors (Electrochem. Soc.), vol. 88-9, pp. 43–54, 1988.
4. J. C. Sturm, “Performance advantages of submicron silicon-on-insulator devices for ULSI,” in MRS Symp. Proc., vol. 107 (Silicon-On-Insulator and Buried Metals in Semiconductors, Boston, MA, Nov. 30–Dec. 3, 1987), pp. 295–307.
5. R. K. Smeltzer and G. L. Schnable, “Material and device technologies for advanced, high performance and radiation-hardened CMOS circuits,” Microelectron. Eng., vol. 8, pp. 79–91, 1988.
6. M. Tack, M. H. Gao, C. Claeys, and G. Declerck, “‘Characterization of different SOI MOS technologies at cryogenic temperatures,” in Proc. 19th ESSDERC Conf. (Berlin, Sept. 1989), pp. 767–770.
7. T. Elewa, F. Balestra, S. Cristoloveanu, A. J. Auberton-Herve, and J. Davis, “Performance of SIMOX transistors at very low temperatures,” in Proc. 1988 IEEE SOS/SOI Technology Workshop (Sea Palms Resort, St. Simons Island, GA, Oct. 1988), p. 77.
8. M. Tack, E. Simoen, X. Q. Li, C. Claeys, and G. Declerck, “The multi-stable behavior of SOI-NMOS transistors at low temperatures,” in Proc. 1988 SOS/SOI Technology Workshop (Sea Palms Resort, St. Simons Island, GA, Oct. 1988), p. 78.
9. D. Wouters, M. Tack, P. Mertens, H. Maes, and C. Claeys, “A comparative study of starting material for SOI device fabrication obtained by different recrystallization procedures and material structures,” in Solid State Devices, G. Soncini and P. U. Calzolari, Eds. Amsterdam, The Netherlands: North-Holland, 1988, pp. 549–552.
10. S. S. Eaton and B. Lalevic, “The effect of floating substrate on the operation of silicon-on-sapphire transistors,” IEEE Trans. Electron Devices, ED-25, p. 907, 1978.
11. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York, NY: Wiley, 1981.
12. H. Lim and J. G. Fossum, “Threshold voltage of thin-film Silicon-On-Insulator (SOI) MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-30, no. 10, pp. 1244–1251, Oct. 1983.
13. M. R. Tack, private communications.
14. J. Frenkel, Phys. Rev., vol. 54, 1983.