The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing

IEEE Transactions on Semiconductor Manufacturing

Volumn 3, Issue 2, 1990, Pages 60-71

  Cunningham, James A ^a  

^a Cunningham Associates ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, VLSI; INTEGRATED CIRCUITS--INSPECTION; PROBABILITY;

CLUSTER PARAMETER; HOLOGRAPHIC WAFER INSPECTION MACHINE; IC YIELD MODELS; NEGATIVE BINOMIAL MODEL; POISSON MODEL;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0025433611     PISSN: 08946507     EISSN: 15582345     Source Type: Journal    
DOI: 10.1109/66.53188     Document Type: Article

References (15)

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