The Cache DRAM Architecture: A DRAM with an On-Chip Cache Memory

IEEE Micro

Volumn 10, Issue 2, 1990, Pages 14-25

  Hidaka, Hideto ^a   Matsuda, Yoshio ^a   Asakura, Mikio ^a   Fujishima, Kazuyasu ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTERS, MICROCOMPUTER--CIRCUITS;

CACHE DRAM ARCHITECTURE; ERROR CHECKING/CORRECTION; ON-CHIP CACHE MEMORY; SOFT ERROR RATE;

DATA STORAGE, DIGITAL;

EID: 0025419834     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.52944     Document Type: Article

References (8)

1. W.M. Regitz et al., “A Three-Transistor-Cell, 1024 bit 500 ns MOS RAM,” ISSCC Digest of Technical Papers, Feb. 1970, pp. 42–43.
2. T. Watanabe et al., “An 8K Byte Intelligent Cache Memory,” ISSCC Digest of Technical Papers, Feb. 1987, pp. 266–267.
3. M. Asakura et al., “An Experimental 1Mb Cache DRAM with ECC,” Symp. VLSI Circuits Digest of Technical Papers, 1989, pp. 43–44.
4. A.J. Smith, “Cache Memories,” Computing Surveys, Vol. 14, No. 3, 1982, pp. 473–530.
5. J.R. Goodman et al., “The Use of Static Column RAM as a Memory Hierarchy,” 11th Int’I Symp. Computer Architecture, 1984, pp. 167–174.
6. M.D. Hill et al., “Experimental Evaluation of On-Chip Microprocessor Cache Memories,” 11th Int–l Symp. Computer Architecture, 1984, pp. 158–166.
7. T. Mano et al., “Circuit Technologies for 16Mb DRAMs,” ISSCC Digest of Technical Papers, Feb. 1970, pp. 42–43.
8. H. Kotani et al., “4Mbit DRAM Design Including 16-Bit-Concurrent ECC,” Symp. VLSI Circuits Digest of Technical Papers, 1987, pp. 87–88.