Computing Optimal Test Sequences from Complete Test Sets for Stuck-Open Faults in CMOS Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 9, Issue 3, 1990, Pages 329-331

  Chakravarty, S ^a   Ravi, S S ^b  

^a UNIVERSITY AT BUFFALO   (United States)

^b STATE UNIVERSITY OF NEW YORK   (United States)

Author keywords

CMOS circuits; substring; superstring; test sequence; transistor stuck open faults

Indexed keywords

INTEGRATED CIRCUIT TESTING--COMPUTER AIDED ANALYSIS; LOGIC CIRCUITS--TESTING;

CMOS CIRCUITS; COMPUTER AIDED TESTING; OPTIMAL TEST SEQUENCES; STUCK-OPEN FAULTS; TEST VECTORS; VLSI FABRICATION;

INTEGRATED CIRCUITS, VLSI;

EID: 0025404023     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.46808     Document Type: Article

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