Fast and Smooth Highly Nonlinear Multidimensional Table Models for Device Modeling

IEEE Transactions on Circuits and Systems

Volumn 37, Issue 3, 1990, Pages 335-346

  Meijer, Peter B L ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC CIRCUITS--COMPUTER SIMULATION; MATHEMATICAL TECHNIQUES--EIGENVALUES AND EIGENFUNCTIONS;

EBERS-MOLL BIPOLAR TRANSISTOR; GLASMOST MOSFET MODEL; SOFTWARE PACKAGE PHILPAC;

TRANSISTORS;

EID: 0025403428     PISSN: 00984094     EISSN: None     Source Type: Journal    
DOI: 10.1109/31.52727     Document Type: Article

References (22)

1. Ph. E. Allen and K. S. Yoon, “A table look-up MOSFET model for analog applications,” in Proc. Int. Conf. Computer-Aided Design, Santa Clara, CA, pp. 124–127, Nov. 1988.
2. J. A. Barby, “Multidimensional splines for modeling FET nonlinearities,” Thesis UW/ICR 86–01, Univ. of Waterloo, Canada, 1986.
3. J. A. Barby, J. Vlach, and K. Singhal, “Polynomial splines for MOSFET model approximation,” IEEE Trans. Computer-Aided Design, vol. 7, pp. 557–566, May 1988.
4. G. Bischoff and J. P. Krusius, “Technology independent device modeling for simulation of integrated circuits for FET technologies,” IEEE Trans. Computer-Aided Design, vol. CAD-4, pp. 99–109, Jan. 1985.
5. C. de Boor, A Practical Guide to Splines. Berlin, Germany: Springer-Verlag, 1978.
6. J. L. Burns, “Empirical MOSFET models for circuit simulation,” Mem. No. UCB/ERL M84/43, Univ. Calif. Berkeley, May 1984.
7. L. O. Chua and A.-C. Deng, “Canonical piecewise-linear modeling,” IEEE Trans. Circuits Syst., vol. CAS-33, pp. 511–525, May 1986.
8. W. M. Coughran, E. Grosse and D. J. Rose, “Variation diminishing splines in simulation,” SIAM J. Sci. Stat. Comput., vol. 7, pp. 696–705, Apr. 1986.
9. D. Divekar, D. Ryan, J. Chan, and J. Deutsch, “Fast and accurate table look-up MOSFET model for circuit simulation,” in Proc. Custom Integrated Circuits Conf., Rochester, NY, pp. 621–623, May 1986.
10. J. J. Ebers and J. L. Moll, “Large-signal behavior of junction transistors,” Proc. IRE, vol. 42, pp. 1761–1772, Dec. 1954.
11. A. R. Forrest, “On Coons and other methods for the representation of curved surfaces,” Comput. Graph. Image Proc., vol. 1, pp. 341–359, 1972.
12. J. L. Huertas and A. Rueda, “Sectionwise piecewise polynomial functions: Applications to the analysis and synthesis of nonlinear n-Port networks,” IEEE Trans. Circuits Syst., vol. CAS-31, pp. 897–906, Oct. 1984.
13. Y.-H. Jun and S.-B. Park, “Piecewise polynomial models for MOSFET dc characteristics with continuous first order derivative,” in Proc. Int. Symp. on Circuits and Systems, Espoo, Finland, pp. 2589–2592, June 1988.
14. M. Marcus and H. Mine, A Survey of Matrix Theory and Matrix Inequalities vol. 14, Boston, MA: Prindle, Weber, and Schmidt, 1964.
15. P. B. L. Meijer, “Table models for device modelling,” in Proc. Int. Symp. on Circuits and Systems, Espoo, Finland, pp. 2593–2596, June 1988.
16. K. J. Narendra, D. Agnew and M. S. Nakhla, “Two-dimensional table look-up MOSFET model,” in Proc. Int. Conf. on Computer-Aided Design, Santa Clara, CA, pp. 201–203, Sept. 1983.
17. K.-G. Rauh, “A table model for circuit simulation,” in Proc. Twelfth European Solid-State Circuits Conf., Delft, The Netherlands, pp. 211–213, 1986.
18. A. R. Rofougaran, B. Furman, and A. A. Abidi, “Accurate analog modeling of short channel FETs based on table lookup,” in Proc. Int. Symp. on Circuits and Systems, Espoo, Finland, pp. 413–416, June 1988.
19. M. F. Sevat, “GLASMOST: A MOSFET model of high numerical quality,” in Proc. Int. Symp. on Circuits and Systems, Espoo, Finland, pp. 2597–2600, June 1988.
20. T. Shima, “Device and circuit simulator integration techniques,” in W. L. Engl, ed., Process and Device Modeling. Amsterdam, The Netherlands: North-Holland, 1986, ch. 14, pp. 433–459.
21. P. Subramaniam, “Table models for timing simulation,” Proc. Custom Integrated Circuits Conf., Rochester, NY, pp. 310–314, May 1984.
22. G. T. Wright, “Physical and CAD models for the implanted-chan-nel VLSI MOSFET,” IEEE Trans. Electron Devices, vol. ED-34, pp. 823–833, Apr. 1987.