LAN interface chip and mixed-signal testing developments

IBM Journal of Research and Development

Volumn 34, Issue 2-3, 1990, Pages 428-441

  Van Horn, J J ^a   Waller, R A ^a   Prilik, R J ^a   Bocash, K C ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT TESTING; PHASE LOCKED LOOPS;

LATCH-BASED BOUNDARIES; LOCAL AREA NETWORK (LAN); MIXED-SIGNAL TESTING; SEMICONDUCTOR CHIP; WAFER TESTING; YIELD LEARNING;

COMPUTER NETWORKS;

EID: 0025401585     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.342.0428     Document Type: Article

References (10)