-
1
-
-
84937350881
-
A telemetering system by code modulation—Delta-sigma modulation
-
Sept.
-
H. Inose, Y. Yasuda, and J. Murakami, “A telemetering system by code modulation—Delta-sigma modulation,” IRE Trans. Space Electron. Telem., vol. SET-8, pp. 204–209, Sept. 1962.
-
(1962)
IRE Trans. Space Electron. Telem.
, vol.SET-8
, pp. 204-209
-
-
Inose, H.1
Yasuda, Y.2
Murakami, J.3
-
2
-
-
0022239639
-
MOS ADC-filter combination that does not require precision analog components
-
Feb.
-
M. W. Hauser, P. J. Hurst, and R. W. Brodersen, “MOS ADC-filter combination that does not require precision analog components,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 80–82, Feb. 1985.
-
(1985)
IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers
, pp. 80-82
-
-
Hauser, M.W.1
Hurst, P.J.2
Brodersen, R.W.3
-
3
-
-
0019597375
-
Single-chip per channel CODEC with filters utilizing delta-sigma modulation
-
Aug.
-
T. Misawa, J. E. Iwersen, L. J. Loporcaro, and J. G. Ruch, “Single-chip per channel CODEC with filters utilizing delta-sigma modulation,” IEEE J. Solid-State Circuits, vol. SC-16, pp. 331–341, Aug. 1981.
-
(1981)
IEEE J. Solid-State Circuits
, vol.SC-16
, pp. 331-341
-
-
Misawa, T.1
Iwersen, J.E.2
Loporcaro, L.J.3
Ruch, J.G.4
-
4
-
-
0022907085
-
A 12-bit sigma-delta analog-to-digital converter with 15 MHz clock rate
-
Dec.
-
R. Koch, B. Heise, F. Eckbauer, E. Engelhardt, J. A. Fisher, and F. Parzefall, “A 12-bit sigma-delta analog-to-digital converter with 15 MHz clock rate,” IEEE J. Solid-State Circuits, vol. SC-21, pp. 1003–1009, Dec. 1986.
-
(1986)
IEEE J. Solid-State Circuits
, vol.SC-21
, pp. 1003-1009
-
-
Koch, R.1
Heise, B.2
Eckbauer, F.3
Engelhardt, E.4
Fisher, J.A.5
Parzefall, F.6
-
5
-
-
0023537896
-
A 16b oversampling A/D conversion technology using triple integration noise shaping
-
Feb.
-
Y. Matsuya, K. Uchimura, A. Iwata, T. Kobyashi, and M. Ishikawa, “A 16b oversampling A/D conversion technology using triple integration noise shaping,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 48–49, Feb. 1987.
-
(1987)
IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers
, pp. 48-49
-
-
Matsuya, Y.1
Uchimura, K.2
Iwata, A.3
Kobyashi, T.4
Ishikawa, M.5
-
6
-
-
84941538134
-
ZSIM: A table-based Z-domain simulator for delta-sigma modulators
-
North Carolina State Univ.
-
G. T. Brauns, “ZSIM: A table-based Z-domain simulator for delta-sigma modulators,” Master's thesis, North Carolina State Univ., 1987.
-
(1987)
Master's thesis
-
-
Brauns, G.T.1
-
7
-
-
0023593856
-
ZSIM: A nonlinear Z-domain simulator for delta-sigma modulators
-
Nov.
-
G. T. Brauns, M. B. Steer, S. H. Ardalan, and J. J. Paulos, “ZSIM: A nonlinear Z-domain simulator for delta-sigma modulators,” in Proc. IEEE Int. Conf. on Computer-Aided Design, pp. 538–541, Nov. 1987.
-
(1987)
Proc. IEEE Int. Conf. on Computer-Aided Design
, pp. 538-541
-
-
Brauns, G.T.1
Steer, M.B.2
Ardalan, S.H.3
Paulos, J.J.4
-
8
-
-
0022315467
-
Measurement and modeling of charge feedthrough in n-channel MOS analog switches
-
Dec.
-
W. B. Wilson, H. Z. Massoud, E. J. Swanson, R. T. George, Jr., and R. B. Fair, “Measurement and modeling of charge feedthrough in n-channel MOS analog switches,” IEEE J. Solid-State Circuits, pp. 1206–1212, Dec. 1985.
-
(1985)
IEEE J. Solid-State Circuits
, pp. 1206-1212
-
-
Wilson, W.B.1
Massoud, H.Z.2
Swanson, E.J.3
George, R.T.4
Fair, R.B.5
-
10
-
-
0020180895
-
CAzM: A circuit analyzer with macromodeling
-
W. M. Coughran, Jr., E. H. Grosse, and D. J. Roser. “CAzM: A circuit analyzer with macromodeling,” IEEE Trans. Electron Devices, vol. ED-30, pp. 1207–1213, 1983.
-
(1983)
IEEE Trans. Electron Devices
, vol.ED-30
, pp. 1207-1213
-
-
Coughran, W.M.1
Grosse, E.H.2
Roser, D.J.3
-
11
-
-
84941538135
-
Duke release CAzM: Users guide
-
Duke Univ., June
-
D. J. Erdman, “Duke release CAzM: Users guide,” Tech. Rep. CS-1987-24, Duke Univ., June 1987.
-
(1987)
Tech. Rep. CS-1987-24
-
-
Erdman, D.J.1
-
12
-
-
0018027059
-
A charge-oriented model for MOS transistor capacitances
-
Oct.
-
D. E. Ward and R. W. Dutton, “A charge-oriented model for MOS transistor capacitances,” IEEE J. Solid-State Circuits, vol. SC-13, pp. 703–707, Oct. 1978.
-
(1978)
IEEE J. Solid-State Circuits
, vol.SC-13
, pp. 703-707
-
-
Ward, D.E.1
Dutton, R.W.2
-
13
-
-
0023434904
-
Realistic worst-case parameters for circuit simulation
-
Oct.
-
P. Yang, B. D. Epler, P. K. Chatterjee, P. Tuohyand, A. Gribben, A. J. Walton, and J. M. Robertson,” Realistic worst-case parameters for circuit simulation,” IEEE Proc., vol. 134, pp. 137–140, Oct. 1987.
-
(1987)
IEEE Proc.
, vol.134
, pp. 137-140
-
-
Yang, P.1
Epler, B.D.2
Chatterjee, P.K.3
Tuohyand, P.4
Gribben, A.5
Walton, A.J.6
Robertson, J.M.7
|