A Parallel Branch and Bound Algorithm for Test Generation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 9, Issue 3, 1990, Pages 313-322

  Patil, Srinivas ^a   Banerjee, Prithviraj ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

hypercube multiprocessors; implicit enumeration; parallel processing; parallel search; Test generation

Indexed keywords

COMPUTER SYSTEMS, DIGITAL--PARALLEL PROCESSING; INTEGRATED CIRCUIT TESTING--COMPUTER AIDED ANALYSIS; LOGIC CIRCUITS--TESTING;

FAULT COVERAGE; PARALLEL TEST GENERATION; TEST GENERATION ALGORITHM; VLSI CIRCUITS;

INTEGRATED CIRCUITS, VLSI;

EID: 0025399222     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.46806     Document Type: Article

References (28)

1. H. Fujiwara and S. Toida, “The complexity of fault detection: An approach to design for testability,” in Proc. 12th Int. Symp. Fault Tolerant Computing, pp. 101–108, June 1982.
2. J. P. Roth, “Diagnosis of automata failures: A calculus and a method,” IBM J. Res. Develop., vol. 10, pp. 278–291, July 1966.
3. P. Goel, “An implicit enumeration algorithm to generate tests for combinational logic circuits,” IEEE Trans. Comput., vol. C-30, pp. 215–222, Mar. 1981.
4. H. Fujiwara and T. Shimono, “On the acceleration of test generation algorithms,” IEEE Trans. Comput., vol. C-32, pp. 1137–1144, Dec. 1983.
5. K. T. Cheng and V. D. Agrawal, “A simulation-based directed search method for test generation,” in Proc. Int. Conf. Computer Design (ICCD-87), pp. 48–51, Oct. 1987.
6. A. Motohara, K. Nishimura, H. Fujiwara, and I. Shirakawa, “A parallel scheme for test pattern generation,” in Proc. Int. Conf. CAD (ICCAD-86), pp. 156–159, Nov. 1986.
7. G. A. Kramer, “Employing massive parallelism in digital ATPG algorithms,” in Proc. 1983 Int. Test Conf., pp. 108-114, 1983.
8. T. S. Abdelrahman and T. N. Mudge, “Parallel branch and bound algorithms on hypercube multiprocessors,” in Proc. Third Conf. on Hypercube and Concurrent Computers and Applications, vol. II, pp. 1492–1499, Jan. 1988.
9. V. N. Rao and V. Kumar, “Parallel depth first search. Part I: Implementation,” Int. J. Parallel Programming, vol. 16, 1987.
10. —, “Parallel depth first search, Part II: Analysis,” Int. J. Parallel Programming, vol. 16, 1987.
11. S. B. Akers, C. Joseph, and B. Krishnamurfhy, ”On the role of independent fault sets in the generation of minimal test sets,” in Proc. IEEE Int. Test Conf., pp. 1100–1107, 1987.
12. S. Patel and J. Patel, “Effectiveness of heuristics measures for automatic test pattern generation,” in Proc. 23rd Design Automation Conf., pp. 547–552, 1986.
13. S. J. Chandra and J. H. Patel, “Experimental evaluation of testability measures for test generation,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 93–98, Jan. 1989.
14. —, “Test generation in a parallel processing environment,” in Proc. IEEE Int. Conf. Computer Design (1CCD-88), Oct. 1988.
15. D. DeGroot, “Restricted and parallelism,” in Proc. Int. Conf. Fifth General Computing Systems, pp. 471–478, 1984.
16. J. S. Conery, “The and/or process model for parallel interpretation of logic programs,” Tech. Rep. 204, Univ. of Calif., Irvine, June 1983.
17. G. J. Li and B. W. Wah, “MAN1P-2: A multicomputer architecture for evaluating logic programs,” in Proc. Int. Conf. Parallel Processing, pp. 123–130, 1985.
18. B. W. Wah, G. J. Li, and C. F. Yu, “Multiprocessing of combinatorial search problems,” IEEE Computer, vol. 18, pp. 93–108, June 1985.
19. H. K. Tony Ma, S. Devadas, and A. Sangiovanni-Vincentelli, “Logic verification algorithms and their parallel implementation,” in Proc. 24th ACM/IEEE Design Automation Conf., pp. 283–290, 1987.
20. L. H. Goldstein and E. L. Thigpen, “SCOAP: Sandia controllability/ observability analysis program,” in Proc. 17th ACM/IEEE Design Automation Conf., 1980.
21. R. G. Bennetts, Design of Testable Logic Circuits. London, U.K.: Addison Wesley, 1984.
22. S. C. Seth, L. Pan, and V. D. Agrawal, “PREDICT—Probabilistic estimation of digital circuit testability,” in Proc. Int. Symp. Fault Tolerant Computing, pp. 220—225, June 1985.
23. A. Ivanov and V. K. Agarwal, “Testability measures—What do they do for ATPG?” in Proc. 1986 Int. Test Conf., pp. 129–138, Sept. 1986.
24. V. K. Janakiram, D. P. Agrawal, and R. Mehrotra, “Randomized parallel algorithms for prolog programs and backtracking applications,” in Proc. Int. Conf. Parallel Processing (ICPP-87), pp. 278–281, 1987.
25. F. Brglez and H. Fujiwara, “Neutral netlist of ten combinational benchmark circuits and a target translator in Fortran,” Proc. IEEE Int. Symp. Circuits and Systems, June 1985.
26. W. T. Cheng, “Split circuit model for test generation,” in Proc. 25th ACM/IEEE Design Automation Conf., pp. 96–101, 1988.
27. T. Kirkland and M. R. Mercer, “A topological search algorithm for ATPG,” in Proc. 24th ACM/IEEE Design Automation Conf., pp. 502–508, 1987.
28. M. H. Schulz and E. Aufh, “Advanced automatic test pattern generation and redundancy identification techniques,” in Proc. Int. Symp. Fault Tolerant Comput., pp. 30–35, June 1988.