Jitter Analysis of High-Speed Sampling Systems

IEEE Journal of Solid-State Circuits

Volumn 25, Issue 1, 1990, Pages 220-224

  Shinagawa, Mitsuru ^a   Akazawa, Yukio ^a   Wakimoto, Tsutomu ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA CONVERSION, ANALOG TO DIGITAL;

CIRCUIT JITTER; CLOCK JITTER; HIGH-SPEED SAMPLING SYSTEMS; JITTER ANALYSIS; SAMPLE-AND-HOLD CIRCUITS; SIGNAL JITTER;

ELECTRONIC CIRCUITS, SWITCHING;

EID: 0025387944     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.50307     Document Type: Article

References (5)

1. Y. Matsuya et. al., “A 16-bit oversampling A-to-D conversion technology using triple-integration noise shaping,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 921–929, Dec. 1987.
2. T. Wakimoto et. al., “Si bipolar 2-GHz 6-bit flash A/D conversion LSI,” IEEE J. Solid-State Circuits, vol. 23, pp. 1345–1350, Dec. 1988.
3. M. Shinagawa et al., “Jitter measurement method of sampling system,” in Proc. Nat. Conv. IECE Jpn., 1989, p. C-334.
4. M. Shinagawa et al., “Jitter analysis of high-speed sampling systems,” in VLSI Circuits Dig. Tech. Paper, 1989, pp. 95-96.
5. J. A. Barns et al., “Characterization of frequency stability,” IEEE Trans. Instrum. Meas., vol. IM-20, no. 2, pp. 105-120, 1971.