A VLSI Design for Computing Exponentiations in GF(2m) and Its Application to Generate Pseudorandom Number Sequences

IEEE Transactions on Computers

Volumn 39, Issue 2, 1990, Pages 258-262

  Wang, Charles C ^a   Pei, Dingyi ^b  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

^b INSTITUTE OF APPLIED MATHEMATICS   (China)

Author keywords

Finite field exponentiation; Massey Omura multiplier; normal basis; pseudorandom number sequence; VLSI

Indexed keywords

COMPUTER PROGRAMMING--ALGORITHMS; LOGIC CIRCUITS--DESIGN; MATHEMATICAL STATISTICS--RANDOM NUMBER GENERATION;

EXPONENTIATIONS; GALOIS FIELDS; PSEUDORANDOM NUMBER SEQUENCES;

INTEGRATED CIRCUITS, VLSI;

EID: 0025387890     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.45211     Document Type: Article

References (7)

1. J. L. Massey and J. K. Omura, “Computational method and apparatus for fine field arithmetic,” U.S. Patent Application, in 1981.
2. C. C. Wang et al., “VLSI architecture for computing multiplications and inverses in GF(2 m),” IEEE Trans. Comput., vol. C-34, no. 8, Aug. 1985.
3. R. C. Dixon, Spread Spectrum Systems. New York: Wiley, 1976.
4. F. J. MacWilliams and N. J. A. Sloane, The Theory of Error-Correcting Codes. New York: North-Holland, 1977.
5. M. Perlman, “Periodic binary sequence generators: Very large scale integrated (VLSI) circuits considerations,” JPL Publ. 85-7, Dec. 1984.
6. W. W. Peterson and E. J. Weldon, Jr., Error-Correcting Codes. Cambridge, MA: MIT Press, 1972.
7. S. Berkovits, J. Kowalchuk, and B. Schanning, “Implementing public key scheme,” IEEE Commun. Mag., vol. 17, pp. 2-3, May 1979.