A Voltage-Controllable Linear MOS Transconductor Using Bias Offset Technique

IEEE Journal of Solid-State Circuits

Volumn 25, Issue 1, 1990, Pages 315-317

  Wang, Zhenhua ^a   Guggenbühl, Walter ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

BIAS OFFSET TECHNIQUE; CURRENT MIRROR; DIFFERENTIAL TRANSISTOR PAIRS; LARGE-SIGNAL MOS TRANSCONDUCTOR; LINEAR MOS TRANSCONDUCTOR; MOBILITY REDUCTION;

TRANSISTORS, FIELD EFFECT;

SEMICONDUCTOR DEVICES, MOS;

EID: 0025384744     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.50321     Document Type: Article

References (6)

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3. G. Merckel. J. Borel. and N. Cupcea. “An accurate large-signal MOS transistor model for use in computer-aided design.” IEEE Trans. Electron Devices. vol. ED-19, pp. 681–690. 1972.
4. M. Banu and Y. Tsividis, “Floating voltage-controlled resistors in MOS technology.” Electron. Lett., vol. 18. pp. 678–679. 1982.
5. R. R. Torrance, T. R. Viswanathan. and J. V. Hanson. “CMOS voltage to current transducers.” IEEE Trans. Circuits Syst., vol. CAS-32. pp. 1097–1104. 1985.
6. F. Krummenacher and N. Joehl. “A 4-MHz CMOS continuous-time filter with on-chip automatic tuning,” IEEE J. Solid-State Circuits, vol. 23. pp. 750–758. 1988.