Table-Based Modeling of Delta-Sigma Modulators Using ZSIM

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 9, Issue 2, 1990, Pages 142-150

  Brauns, Gregory T ^a   Bishop, Richard J ^a,b   Steer, Michael B ^a   Paulos, John J ^a   Ardalan, Sasan Houston ^a  

^a NORTH CAROLINA STATE UNIVERSITY   (United States)

^b INTERSIL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA CONVERSION, ANALOG TO DIGITAL; ELECTRIC FILTERS, DIGITAL; MATHEMATICAL TECHNIQUES--DIFFERENCE EQUATIONS;

DELTA-SIGMA MODULATORS; DIFFERENCE EQUATION SIMULATIONS; LINEAR TABLE INTERPOLATION; NONLINEAR Z-DOMAIN SIMULATOR; SOFTWARE PACKAGE ZSIM;

MODULATORS;

EID: 0025384501     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.46780     Document Type: Article

References (26)

1. H. Inose, Y. Yasuda, and J. Murakami, “A telemetering system by code modulation—delta-sigma modulation,” IRE Trans. Space Electron. Telemetry, vol. SET-8, pp. 204–209, Sept. 1962.
2. M. W. Hauser, P. J. Hurst, and R. W. Brodersen, “MOS ADC-filter combination that does not require precision analog components,” in IEEE ISSCC Dig. Tech. Papers, pp. 80–82, Feb. 1985.
3. T. Misawa, J. E. Iwersen, L. J. Loporcaro, and J. G. Ruch, “Singlechip per channel CODEC with filters utilizing △-∑ modulation,” IEEE J. Solid-State Circuits, vol. SC-16, pp. 333–341, Aug. 1981.
4. R. Koch, B. Heise, F. Eckbauer, E. Engelhardt, J. A. Fisher, and F. Parzefall, “A 12-bit sigma-delta analog-to-analog converter with a 15-MHz clock rate,” IEEE J. Solid-State Circuits, vol. SC-21, pp. 1003–1009, Dec. 1986.
5. Y. Matsuya, K. Uchimura, A. Iwata, T. Kobayashi, and M. Ishikawa, “A 16b oversampling A/D conversion technology using triple integration noise shaping,” in IEEE ISSCC Dig. of Tech. Papers, pp. 48–49, Feb. 1987.
6. J. C. Candy and O. J. Benjamin, “The structure of quantization noise from signal-delta modulation,” IEEE Trans. Commun., vol. COM-29, pp. 1316–1323, Sept. 1981.
7. B. P. Agrawal and K. Shenoi, “Design methodology for ∑∆M,” IEEE Trans. Commun., vol. COM-31, pp. 360–370, Mar. 1983.
8. J. C. Candy, “Decimation for sigma delta modulation,” IEEE Trans. Commun., vol. COM-34, pp. 72–76, Jan. 1986.
9. E. Dijkstra, J. Rijmenants, and O. Nys, “A design methodology for decimation filter in sigma delta A/D converters,” in Proc. IEEE Int. Symp. on Circuits and Systems, pp. 479–482, May 1987.
10. R. M. Gray, “Oversampled sigma-delta modulation,” IEEE Trans. on Commun., vol. COM-35, pp. 481–488, May 1987.
11. J. Stonick and S. H. Ardalan, “An improved discrete time model for the analysis of delta sigma modulators with bandlimited Gaussian inputs,” in Proc. Int. Conf. on Communications, pp. 647–751, June 1988.
12. S. H. Ardalan and J. J. Paulos, “Analysis of nonlinear behavior in delta-sigma modulators,” IEEE Trans. Circuits Syst., vol. CAS-34, pp. 593–603, June 1987.
13. L. W. Nagel, “SPICE2: A computer program to simulate semiconductor circuits,” Univ. Cali. at Berkeley, Memo no. ERL-M520, May 1975.
14. M. W. Hauser and R. W. Brodersen, “Circuit and technology considerations for MOS delta-sigma A/D converters,” in IEEE Int. Symp. Circuits and Systems Dig. Tech. Papers, pp. 1310–1315, 1986.
15. J. L. Burns, A. R. Newton, and D. O. Pederson, “Active device table look-up models for circuit simulation,” IEEE Int. Symp. on Circuits and Systems, pp. 250–253, May 1983.
16. K. Sakui, T. Shima, Y. Hayashi, F. Horiguchi, and M. Ogura, “A simplified accurate three-dimensional table look-up MOSFET model for VLSI circuit simulation,” in Proc. IEEE Custom Integrated Circuits Conf., pp. 347–351, May 1985.
17. T. Shima, “Table look-up MOSFET capacitance model for short-channel devices,” IEEE Trans. Computer-Aided Design, vol. CAD-5, pp. 624–632, Oct. 1986.
18. W. M. Coughran, E. H. Grosse, and D. J. Rose, “CAzM: A circuit analyzer with macromodeling,” IEEE Trans. Electron Devices, vol. ED-30, pp. 1207–1213, Sept. 1983.
19. R. H. Jansen, “LINMIC: A CAD package for the layout-oriented design of single- and multi-layer MICs/MMICs up to mm-wave frequencies,” Microwave J., p. 151, Feb. 1986.
20. H. Meleis and P. LeFur, “A novel architecture design for VLSI implementation of an FIR decimation filter,” in IEEE 1CASSP Dig. of Tech. Papers, pp. 1380–1383, Aug. 1985.
21. K. Martin and A. S. Sedra, “Stray-insensitive switched-capacitor filters based on bilinear z-transform,” Electron. Lett., vol. 15, no. 13, pp. 365–366, June 21, 1979.
22. K. Martin, “Improved circuits for the realization of switched-capacitor filters,” IEEE Trans. Circuits Syst., vol. CAS-27, pp. 237–244, Apr. 1980.
23. D. E. Ward and R. W. Dutton, “A charge-oriented model for MOS transistor capacitances,” IEEE J. Solid-State Circuits, vol. SC-13, pp. 703–707, Oct. 1978.
24. P. Yang, B. D. Epier, and P. K. Chatterjee, “An investigation of the charge conservation problem for MOSFET circuit simulation,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 128–138, Feb. 1983.
25. R. J. Bishop, J. J. Paulos, M. B. Steer, and S. H. Ardalan, “Table-based modeling of delta-sigma modulators,” IEEE Trans. Circuits Syst., to be published.
26. F. J. Harris, “On the use of windows for harmonic analysis with the discrete Fourier transform,” Proc. IEEE, vol. 66, pp. 51–83, Jan. 1978.