A Circuit Design to Suppress Asymmetrical Characteristics in High-Density DRAM Sense Amplifiers

IEEE Journal of Solid-State Circuits

Volumn 25, Issue 1, 1990, Pages 36-41

  Yamauchi, Hiroyuki ^a   Yabu, Toshiki ^a   Yamada, Toshio ^a   Inoue, Michihiro ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS - DESIGN; INTEGRATED CIRCUITS - LAYOUT; TRANSISTORS, FIELD EFFECT;

DRAIN CURRENT; HIGH-DENSITY DRAM; LAYOUT AREA; SENSE AMPLIFIERS; SUBMICROMETER GATE LENGTHS; TRANSISTOR PAIRS;

DATA STORAGE, DIGITAL;

EID: 0025382946     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.50281     Document Type: Article

References (9)

1. M. Inoue et. all., “A 16Mb DRAM with an open bit-line architecture,” in ISSCC Dig. Tech. Papers, Feb. 1988. pp. 246–247.
2. S. Odanaka et. al., “A new half-micrometer p-channel MOSFET with efficient punchthrough stops,” IEEE Trans. Electron Devices. vol. ED-33, no. 3, pp. 317–321, Mar. 1986.
3. H. Tanaka et. al., “An effect of oblique ion implantation on DRAM sense amplifier.” in Spring Nat. Conv. Rec. IEIEE, C-330, Apr. 1988, p. 291.
4. T. Yabu et. al., “Improvement of asymmetrical characteristics in submicron CMOS devices,” Trans. IEIEE, part C. pp. 456–462, May 1989.
5. Y. Oowaki et. all., “Analysis of LDD transistor asymmetry susceptibility in VLSI circuits,” in IEDM Tech. Dig., Dec. 1985. pp. 492–495.
6. T. Eimori et. all., “The improvement of LDD MOSFETs characteristics by the oblique-rotating ion implantation,” in 19th Conf. Solid State Devices and Materials Extended Abstr., July 1987, pp. 27–30.
7. W. T. Lynch et. al., “Optimization of the latching pulse for dynamic flip flop sensors.” IEEE J. Solid-State Circuits, vol. SC-9, pp. 49–55, Apr. 1974.
8. T. Furuyama et. all., “A new sense amplifier technique for VLSI dynamic RAMs,” in IEDM Tech. Dig., Dec. 1981, pp. 44–47.
9. H. Yamauchi et. all., “A circuit design to suppress asymmetrical characteristics in 16-Mbit DRAM sense amplifier,” in Synip. VLSI Circuit Tch. Dig., May 1989, pp. 109–110.