Irredundant Sequential Machines Via Optimal Logic Synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 9, Issue 1, 1990, Pages 8-18

  Devadas, Srinivas ^a   Ma, Hi Keung Tony ^b   Newton, A Richard ^b   Sangiovanni Vincentelli, Alberto ^b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC DEVICES--SYNTHESIS;

SEQUENTIAL MACHINES;

SWITCHING THEORY;

EID: 0025263555     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.45852     Document Type: Article

References (14)

1. V. D. Agarwal, S. K. Jain, and D. M. Singer, “Automation in design for testability,” in Proc. Custom Integrated Circuit Conf., May 1984.
2. K. Bartlett, R. K. Brayton, G. D. Hachtel, R. M. Jacoby, C. R. Morrison, R, L. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang, “Multilevel logic minimization using implicit don't cares,” IEEE Trans. Computer-Aided Design, vol. 7, pp. 723–740, June 1988.
3. R. K. Brayton, G. D. Hachtel, Curt McMullen, and A. Sangiovanni-Vincentelli” Logic Minimization Algorithms for VLSI Synthesis. Hingham, MA: Kluwer Academic, 1984.
4. R. K. Brayton and F. Somenzi, “Boolean relations and the incomplete specification of logic networks,” in Proc. VLSI 89, Aug. 1989.
5. M. A. Breuer and A. D. Friedman, Diagnosis and Reliable Design of Digital Systems. Rockville, MD: Computer Science, 1976.
6. S. Devadas, H-K. T. Ma, and A. R. Newton, “On the verification of sequential machines at differing levels of abstraction,” IEEE Trans. Computer-Aided Designer, vol. 2, pp. 713–722, June 1988.
7. S. Devadas, H-K. T. Ma, A. R. Newton, and A. Sangiovanni-Vincentelli, “Mustang: State assignment of finite state machines targeting multilevel logic implementations,” IEEE Trans. Computer-Aided Design, vol. 7, pp. 1290–1300, Dec. 1988.
8. —, “Synthesis and optimization procedures for fully and easily testable sequential machines,” in Proc. Int. Test Conf, pp. 621–630, Sept. 1988.
9. E. B. Eichelberger and T. W. Williams, “A logic design structure for Isi testability,” in Proc. 14th Design Automation Conf, pp. 462–468, June 1977.
10. J. Hartmanis and R. E. Stearns, “Some dangers in the state reduction of sequential machines,” Inform. Com., pp. 252–260, Sept. 1962.
11. F. J. Hill and G. R. Peterson, Introduction to Switching Theory and Logical Design. New York: Wiley 1981.
12. H-K. T. Ma, S. Devadas, A. R. Newton, and A. Sangiovanni-Vincentelli, “Test generation for sequential circuits,” IEEE Trans. Computer-Aided Design, vol. 7, pp. 1081–1093, Oct. 1988.
13. G. De Micheli, R. K. Brayton, and A. Sangiovanni-Vincentelli, “Optimal state assignment of finite state machines,” IEEE Trans. Computer-Aided Design, vol. CAD-5, pp. 269–285, July 1985.
14. M. C. Paul and S. H. Unger, “Minimizing the number of states in incompletely specified sequential circuits,” IRE Trans. Electron. Comput., pp. 356–357, Sept. 1959.