Multiplier Policies For Digital Signal Processing

IEEE ASSP Magazine

Volumn 7, Issue 1, 1990, Pages 6-20

  Ma, Gin Kou ^a   Taylor, Fred J ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS, DIGITAL--MULTIPLYING CIRCUITS; INTEGRATED CIRCUITS, VLSI; LOGIC DESIGN;

CELLULAR ARRAYS; DIGITAL MULTIPLICATION; FIXED-POINT MULTIPLIERS; HOMOMORPHIC SYSTEMS; MODULAR ARITHMETIC; SHIFT/ADD STRUCTURES;

SIGNAL PROCESSING;

EID: 0025225968     PISSN: 07407467     EISSN: None     Source Type: Journal    
DOI: 10.1109/53.45968     Document Type: Article

References (25)

1. S. Waser and M.J. Flynn, Introduction to Arithmetic for Digital Systems Designers, CBS College Publishing, 1982.
2. K. Hwang, Computer Arithmetic Principles, Architecture, and Design, John Wiley & Sons, 1979.
3. J.D. Ullman, Computational Aspects of VLSI, Computer Science Press, Inc., 1984.
4. H.J. Sips, Bit-Sequential Arithmetic for Parallel Processors, IEEE Trans. on Computers, January 1984.
5. N. Kanopoulos, A Bit:Serial Architecture for Digital Signal Processing, IEEE Trans. on Circuits and Systems, March 1985.
6. J. H. McClellan and C. M. Rader, Number Theory in Digital Signal Processing, Prentice-Hall, Inc., 1979.
7. F.J. Taylor, Residue Arithmetic: A Tutorial with Examples, IEEE Trans. on Computers, May 1984.
8. M. C. Vanwormhoudt, Structural Properties of Complex Residue Rings Applied To Number Theoretic Fourier Transforms, IEEE Trans. on ASSP, February 1978.
9. F.J. Taylor, Single Modulus Complex ALU, IEEE Trans. on ASSP, October 1985.
10. F.J. Taylor, A VLSI Residue Arithmetic Multiplier, IEEE Trans. on Computers, June 1982.
11. F.J. Taylor and C.H. Huang, An Autoscale Residue Multiplier, IEEE Trans. on Computers, April 1982.
12. C. Mead and L. Conway, Introduction to VLSI Systems, Addison-Wesley Publishing, Inc., 1980.
13. I. N. Herstern, Topics in Algebra, 2nd Ed., Southwest Book Co., 1975.
14. N.G. Kingsburg and P.J.W. Rayner, Digital Filtering using Logarithmic Arithmetic, Electron. Letts., January 28, 1971.
15. F.J. Taylor, An Extended Precision Logarithmic Number System, IEEE Trans. on ASSP, February 1983.
16. E.E. Swartzlander et al., Sign/Logarithmic Arithmetic for FFT Implementation, IEEE Trans. on Computers, June 1983.
17. G.L. Sicuraza, On Efficient Implementation of 2-D Digital Filters Using Logarithmic Number System, IEEE ASSP, August 1983.
18. F.J. Taylor, A Hybrid Floating Point Logarithmic Number System Processor, IEEE Trans. on Circuits and Systems, January 1985.
19. F.J. Taylor, R. Gill, J. Joseph, and J. Radke, A 20 Bit Logarithmic Number System Processor, IEEE Trans. on Computers, February 1988.
20. E. P. Armendariz and S. McAdam, Elementary Number Theory, McMillan, 1980.
21. A. Peled and B. Liu, A New Hardware Realization of Digital Filters, IEEE Trans. on ASSP, ASSP-27, December 1974.
22. F.J. Taylor, Digital Filter Design Handbook, Marcel Dekker, Inc., NYC, 1984.
23. H.T. Kung and CE. Leiserson, Systolic Arrays (For VLSI), Sparse Matrix Processings, SIAM, pp. 256-282, 1978.
24. F. J. Taylor et al., Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, IEEE Press, 1986.
25. F.J. Taylor and A.S. Rammarayanan, An Efficient Residue-to-Decimal Converter, IEEE Trans. on Circuits and Systems, December 1981.