Parallel Simulated Annealing Algorithms for Cell Placement on Hypercube Multiprocessors

IEEE Transactions on Parallel and Distributed Systems

Volumn 1, Issue 1, 1990, Pages 91-106

  Banerjee, Prithviraj ^a   Jones, Mark Howard ^b   Sargent, Jeff S ^c  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b LUCENT TECHNOLOGIES   (United States)

^c Incredible Technologies ^*  (United States)

Author keywords

Cell placement; error control; hypercube multiprocessors; parallel processing; performance measurements; simulated annealing; VLSI layout

Indexed keywords

COMPUTER PROGRAMMING--ALGORITHMS; INTEGRATED CIRCUITS, VLSI--LAYOUT;

CELL PLACEMENT; HYPERCUBE MULTIPROCESSORS; SIMULATED ANNEALING ALGORITHMS;

COMPUTER SYSTEMS, DIGITAL;

EID: 0025206726     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/71.80128     Document Type: Article

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