A 0.5-μm BiCMOS technology for logic and 4 Mbit-class SRAM's

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1989, Pages 425-428

  Eklund, R ^a   Chapman, R ^a   Wei, C ^a   Blanton, C ^a   Holloway, T ^a   Rodder, M ^a   Graham, J ^a   Terazawa, H ^a   Rao, V ^a   Tran, H ^a   Suzuki, T ^a   Havemann, R ^a   Sundaresan, R ^a   Scott, D ^a   Haken, R ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, CMOS; LOGIC CIRCUITS, NAND; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICES, MOS;

BICMOS TECHNOLOGY; HOT CARRIERS; NAND GATE; NMOS DEVICE; PMOS LOAD DEVICE; SRAM;

DATA STORAGE, DIGITAL;

EID: 0024920408     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)