메뉴 건너뛰기




Volumn 36, Issue 6, 1989, Pages 2229-2238

The effect of circuit topology on radiation-induced latchup

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE, DIGITAL--FIXED; INTEGRATED CIRCUITS;

EID: 0024908419     PISSN: 00189499     EISSN: 15581578     Source Type: Journal    
DOI: 10.1109/23.45429     Document Type: Article
Times cited : (14)

References (18)
  • 2
    • 0021201527 scopus 로고
    • Latchup Model for the Parasitic pnpn Path in Bulk CMOS
    • R. C. Fang and J. L. Moll, “Latchup Model for the Parasitic pnpn Path in Bulk CMOS”, IEEE Trans. Elect. Dev., ED-31, 113 (1984).
    • (1984) IEEE Trans. Elect. Dev , vol.ED-31 , pp. 113
    • Fang, R.C.1    Moll, J.L.2
  • 3
    • 0024610461 scopus 로고
    • A CMOS Model for Computer-Aided Circuit Analysis and Design
    • J. W. Roberts and S. G. Chamberlain, “A CMOS Model for Computer-Aided Circuit Analysis and Design”, IEEE J. of Solid State Circuits, 24, 128 (1989).
    • (1989) IEEE J. of Solid State Circuits , vol.24 , pp. 128
    • Roberts, J.W.1    Chamberlain, S.G.2
  • 4
    • 84939019207 scopus 로고
    • The Dependence of Latch-up on Layout Features in CMOS Integrated Circuits
    • Y. Song, et al., “The Dependence of Latch-up on Layout Features in CMOS Integrated Circuits”, IEEE Trans. Nucl. Sci., NS-33, 1493 (1986).
    • (1986) IEEE Trans. Nucl. Sci , vol.NS-33 , pp. 1493
    • Song, Y.1
  • 5
    • 84939064830 scopus 로고
    • Testing Considerations for Radiation-Induced Latchup
    • M. P. Baze and A. H. Johnston, “Testing Considerations for Radiation-Induced Latchup”, IEEE Trans. Nucl. Sci., NS-34, 1730 (1987).
    • (1987) IEEE Trans. Nucl. Sci , vol.NS-34 , pp. 1730
    • Baze, M.P.1    Johnston, A.H.2
  • 6
    • 0022231773 scopus 로고
    • Experimental Methods for Determining Latchup Paths in Integrated Circuits
    • A. H. Johnston and M. P. Baze, “Experimental Methods for Determining Latchup Paths in Integrated Circuits”, IEEE Trans. Nucl. Sci., NS-32, 4018 (1985).
    • (1985) IEEE Trans. Nucl. Sci , vol.NS-32 , pp. 4018
    • Johnston, A.H.1    Baze, M.P.2
  • 7
    • 0020782196 scopus 로고
    • High Density and Reduced Latchup Susceptibility CMOS Technology for VLSI
    • J. Manoliu, et al., “High Density and Reduced Latchup Susceptibility CMOS Technology for VLSI”, IEEE Elect. Dev. Lett., EDL-4, 233 (1983).
    • (1983) IEEE Elect. Dev. Lett , vol.EDL-4 , pp. 233
    • Manoliu, J.1
  • 8
    • 0023435530 scopus 로고
    • Latchup Performance of Retrograde and Conventional n-Well CMOS Technologies
    • A. G. Lewis, et al., “Latchup Performance of Retrograde and Conventional n-Well CMOS Technologies”, IEEE Trans. Elect. Dev., ED-34 2156 (1987).
    • (1987) IEEE Trans. Elect. Dev , vol.ED-34 , pp. 2156
    • Lewis, A.G.1
  • 9
    • 0024172676 scopus 로고
    • A Distributed Model for Radiation-Induced Latchup
    • R. E. Plaag, M. P. Baze and A. H. Johnston, “A Distributed Model for Radiation-Induced Latchup”, IEEE Trans. Nucl. Sci., NS-35, 1563 (1988).
    • (1988) IEEE Trans. Nucl. Sci , vol.NS-35 , pp. 1563
    • Plaag, R.E.1    Baze, M.P.2    Johnston, A.H.3
  • 10
    • 84939749753 scopus 로고
    • Ed., CMOS3 Cell Library, Addison-Wesley, Reading, MA
    • D. V. Heinbuch, Ed., CMOS3 Cell Library, Addison-Wesley, Reading, MA, 1988.
    • (1988)
    • Heinbuch, D.V.1
  • 11
    • 70350581098 scopus 로고
    • Transient Response of Transistors and Diodes to Ionizing Radiation
    • J. L. Wirth and S. C. Rogers, “Transient Response of Transistors and Diodes to Ionizing Radiation”, IEEE Trans. Nucl. Sci., NS-11, No. 5, 24 (1964).
    • (1964) IEEE Trans. Nucl. Sci , vol.NS-11 , Issue.5 , pp. 24
    • Wirth, J.L.1    Rogers, S.C.2
  • 13
    • 0021482575 scopus 로고
    • Substrate Resistance Calculation for Latchup Modeling
    • K. W. Terrill and C. Hu, “Substrate Resistance Calculation for Latchup Modeling”, IEEE Trans. Elect. Dev., ED-31 1152 (1984).
    • (1984) IEEE Trans. Elect. Dev , vol.ED-31 , pp. 1152
    • Terrill, K.W.1    Hu, C.2
  • 14
    • 0038185073 scopus 로고
    • The Physics and Modeling of Latch-Up and CMOS Integrated Circuits
    • Stanford Univ., Stanford, CA
    • D. B. Estreich, “The Physics and Modeling of Latch-Up and CMOS Integrated Circuits”, Stanford Univ. Report G-201-9, Stanford Univ., Stanford, CA, 1980.
    • (1980) Stanford Univ. Report G-201-9
    • Estreich, D.B.1
  • 15
    • 0018585984 scopus 로고
    • Conductivity Modulation Effects in Diffused Resistors at Very High Dose Rate Levels
    • G. C. Messenger, “Conductivity Modulation Effects in Diffused Resistors at Very High Dose Rate Levels”, IEEE Trans. Nucl. Sci., NS-26, 4725 (1979).
    • (1979) IEEE Trans. Nucl. Sci , vol.NS-26 , pp. 4725
    • Messenger, G.C.1
  • 16
    • 0024665826 scopus 로고
    • Infrared Microscopy Study of Anomalous Latchup Characteristics Due to Current Redistribution in Different Parasitic Paths
    • C. Canali, et al., “Infrared Microscopy Study of Anomalous Latchup Characteristics Due to Current Redistribution in Different Parasitic Paths”, IEEE Trans. Elect. Dev., ED-36, 969 (1989).
    • (1989) IEEE Trans. Elect. Dev , vol.ED-36 , pp. 969
    • Canali, C.1
  • 17
    • 0020910281 scopus 로고
    • Seeing Through the Latchup Window
    • F. N. Coppage, et al., “Seeing Through the Latchup Window”, IEEE Trans. Nucl. Sci., NS-30, 4122 (1983).
    • (1983) IEEE Trans. Nucl. Sci , vol.NS-30 , pp. 4122
    • Coppage, F.N.1
  • 18
    • 0022866616 scopus 로고
    • Latchup Paths in Bipolar Integrated Circuits
    • M. P. Base and A. H. Johnston, “Latchup Paths in Bipolar Integrated Circuits”, IEEE Trans. Nucl. Sci., NS-33, 1499 (1986)
    • (1986) IEEE Trans. Nucl. Sci , vol.NS-33 , pp. 1499
    • Base, M.P.1    Johnston, A.H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.