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Volumn , Issue , 1989, Pages 212-215
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State assignment for initializable synthesis
a a |
Author keywords
[No Author keywords available]
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Indexed keywords
AUTOMATA THEORY;
LOGIC DESIGN;
GATE LEVEL ANALYSIS;
INITIALIZABLE SYNTHESIS;
UNINITIALIZABLE DESIGN;
SWITCHING THEORY;
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EID: 0024891273
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (17)
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References (12)
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